mirror of
https://github.com/c64scene-ar/llvm-6502.git
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c249168837
This commit serializes the sub register indices from the register machine operands. Reviewers: Duncan P. N. Exon Smith git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242084 91177308-0d34-0410-b5e6-96231b3b80d8
586 lines
19 KiB
C++
586 lines
19 KiB
C++
//===- MIParser.cpp - Machine instructions parser implementation ----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the parsing of machine instructions.
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//
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//===----------------------------------------------------------------------===//
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#include "MIParser.h"
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#include "MILexer.h"
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#include "llvm/ADT/StringMap.h"
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#include "llvm/AsmParser/SlotMapping.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/IR/Module.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Support/SourceMgr.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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using namespace llvm;
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namespace {
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/// A wrapper struct around the 'MachineOperand' struct that includes a source
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/// range.
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struct MachineOperandWithLocation {
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MachineOperand Operand;
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StringRef::iterator Begin;
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StringRef::iterator End;
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MachineOperandWithLocation(const MachineOperand &Operand,
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StringRef::iterator Begin, StringRef::iterator End)
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: Operand(Operand), Begin(Begin), End(End) {}
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};
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class MIParser {
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SourceMgr &SM;
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MachineFunction &MF;
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SMDiagnostic &Error;
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StringRef Source, CurrentSource;
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MIToken Token;
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const PerFunctionMIParsingState &PFS;
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/// Maps from indices to unnamed global values and metadata nodes.
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const SlotMapping &IRSlots;
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/// Maps from instruction names to op codes.
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StringMap<unsigned> Names2InstrOpCodes;
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/// Maps from register names to registers.
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StringMap<unsigned> Names2Regs;
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/// Maps from register mask names to register masks.
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StringMap<const uint32_t *> Names2RegMasks;
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/// Maps from subregister names to subregister indices.
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StringMap<unsigned> Names2SubRegIndices;
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public:
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MIParser(SourceMgr &SM, MachineFunction &MF, SMDiagnostic &Error,
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StringRef Source, const PerFunctionMIParsingState &PFS,
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const SlotMapping &IRSlots);
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void lex();
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/// Report an error at the current location with the given message.
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///
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/// This function always return true.
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bool error(const Twine &Msg);
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/// Report an error at the given location with the given message.
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///
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/// This function always return true.
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bool error(StringRef::iterator Loc, const Twine &Msg);
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bool parse(MachineInstr *&MI);
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bool parseMBB(MachineBasicBlock *&MBB);
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bool parseRegister(unsigned &Reg);
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bool parseRegisterFlag(unsigned &Flags);
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bool parseSubRegisterIndex(unsigned &SubReg);
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bool parseRegisterOperand(MachineOperand &Dest, bool IsDef = false);
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bool parseImmediateOperand(MachineOperand &Dest);
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bool parseMBBReference(MachineBasicBlock *&MBB);
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bool parseMBBOperand(MachineOperand &Dest);
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bool parseGlobalAddressOperand(MachineOperand &Dest);
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bool parseMachineOperand(MachineOperand &Dest);
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private:
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/// Convert the integer literal in the current token into an unsigned integer.
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///
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/// Return true if an error occurred.
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bool getUnsigned(unsigned &Result);
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void initNames2InstrOpCodes();
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/// Try to convert an instruction name to an opcode. Return true if the
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/// instruction name is invalid.
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bool parseInstrName(StringRef InstrName, unsigned &OpCode);
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bool parseInstruction(unsigned &OpCode);
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bool verifyImplicitOperands(ArrayRef<MachineOperandWithLocation> Operands,
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const MCInstrDesc &MCID);
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void initNames2Regs();
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/// Try to convert a register name to a register number. Return true if the
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/// register name is invalid.
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bool getRegisterByName(StringRef RegName, unsigned &Reg);
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void initNames2RegMasks();
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/// Check if the given identifier is a name of a register mask.
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///
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/// Return null if the identifier isn't a register mask.
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const uint32_t *getRegMask(StringRef Identifier);
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void initNames2SubRegIndices();
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/// Check if the given identifier is a name of a subregister index.
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///
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/// Return 0 if the name isn't a subregister index class.
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unsigned getSubRegIndex(StringRef Name);
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};
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} // end anonymous namespace
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MIParser::MIParser(SourceMgr &SM, MachineFunction &MF, SMDiagnostic &Error,
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StringRef Source, const PerFunctionMIParsingState &PFS,
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const SlotMapping &IRSlots)
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: SM(SM), MF(MF), Error(Error), Source(Source), CurrentSource(Source),
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Token(MIToken::Error, StringRef()), PFS(PFS), IRSlots(IRSlots) {}
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void MIParser::lex() {
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CurrentSource = lexMIToken(
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CurrentSource, Token,
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[this](StringRef::iterator Loc, const Twine &Msg) { error(Loc, Msg); });
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}
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bool MIParser::error(const Twine &Msg) { return error(Token.location(), Msg); }
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bool MIParser::error(StringRef::iterator Loc, const Twine &Msg) {
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assert(Loc >= Source.data() && Loc <= (Source.data() + Source.size()));
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Error = SMDiagnostic(
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SM, SMLoc(),
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SM.getMemoryBuffer(SM.getMainFileID())->getBufferIdentifier(), 1,
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Loc - Source.data(), SourceMgr::DK_Error, Msg.str(), Source, None, None);
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return true;
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}
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bool MIParser::parse(MachineInstr *&MI) {
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lex();
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// Parse any register operands before '='
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// TODO: Allow parsing of multiple operands before '='
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MachineOperand MO = MachineOperand::CreateImm(0);
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SmallVector<MachineOperandWithLocation, 8> Operands;
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if (Token.isRegister() || Token.isRegisterFlag()) {
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auto Loc = Token.location();
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if (parseRegisterOperand(MO, /*IsDef=*/true))
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return true;
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Operands.push_back(MachineOperandWithLocation(MO, Loc, Token.location()));
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if (Token.isNot(MIToken::equal))
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return error("expected '='");
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lex();
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}
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unsigned OpCode;
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if (Token.isError() || parseInstruction(OpCode))
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return true;
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// TODO: Parse the instruction flags and memory operands.
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// Parse the remaining machine operands.
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while (Token.isNot(MIToken::Eof)) {
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auto Loc = Token.location();
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if (parseMachineOperand(MO))
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return true;
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Operands.push_back(MachineOperandWithLocation(MO, Loc, Token.location()));
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if (Token.is(MIToken::Eof))
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break;
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if (Token.isNot(MIToken::comma))
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return error("expected ',' before the next machine operand");
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lex();
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}
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const auto &MCID = MF.getSubtarget().getInstrInfo()->get(OpCode);
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if (!MCID.isVariadic()) {
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// FIXME: Move the implicit operand verification to the machine verifier.
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if (verifyImplicitOperands(Operands, MCID))
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return true;
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}
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// TODO: Check for extraneous machine operands.
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MI = MF.CreateMachineInstr(MCID, DebugLoc(), /*NoImplicit=*/true);
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for (const auto &Operand : Operands)
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MI->addOperand(MF, Operand.Operand);
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return false;
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}
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bool MIParser::parseMBB(MachineBasicBlock *&MBB) {
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lex();
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if (Token.isNot(MIToken::MachineBasicBlock))
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return error("expected a machine basic block reference");
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if (parseMBBReference(MBB))
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return true;
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lex();
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if (Token.isNot(MIToken::Eof))
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return error(
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"expected end of string after the machine basic block reference");
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return false;
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}
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static const char *printImplicitRegisterFlag(const MachineOperand &MO) {
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assert(MO.isImplicit());
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return MO.isDef() ? "implicit-def" : "implicit";
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}
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static std::string getRegisterName(const TargetRegisterInfo *TRI,
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unsigned Reg) {
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assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "expected phys reg");
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return StringRef(TRI->getName(Reg)).lower();
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}
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bool MIParser::verifyImplicitOperands(
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ArrayRef<MachineOperandWithLocation> Operands, const MCInstrDesc &MCID) {
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if (MCID.isCall())
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// We can't verify call instructions as they can contain arbitrary implicit
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// register and register mask operands.
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return false;
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// Gather all the expected implicit operands.
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SmallVector<MachineOperand, 4> ImplicitOperands;
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if (MCID.ImplicitDefs)
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for (const uint16_t *ImpDefs = MCID.getImplicitDefs(); *ImpDefs; ++ImpDefs)
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ImplicitOperands.push_back(
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MachineOperand::CreateReg(*ImpDefs, true, true));
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if (MCID.ImplicitUses)
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for (const uint16_t *ImpUses = MCID.getImplicitUses(); *ImpUses; ++ImpUses)
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ImplicitOperands.push_back(
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MachineOperand::CreateReg(*ImpUses, false, true));
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const auto *TRI = MF.getSubtarget().getRegisterInfo();
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assert(TRI && "Expected target register info");
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size_t I = ImplicitOperands.size(), J = Operands.size();
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while (I) {
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--I;
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if (J) {
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--J;
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const auto &ImplicitOperand = ImplicitOperands[I];
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const auto &Operand = Operands[J].Operand;
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if (ImplicitOperand.isIdenticalTo(Operand))
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continue;
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if (Operand.isReg() && Operand.isImplicit()) {
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return error(Operands[J].Begin,
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Twine("expected an implicit register operand '") +
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printImplicitRegisterFlag(ImplicitOperand) + " %" +
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getRegisterName(TRI, ImplicitOperand.getReg()) + "'");
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}
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}
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// TODO: Fix source location when Operands[J].end is right before '=', i.e:
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// insead of reporting an error at this location:
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// %eax = MOV32r0
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// ^
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// report the error at the following location:
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// %eax = MOV32r0
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// ^
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return error(J < Operands.size() ? Operands[J].End : Token.location(),
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Twine("missing implicit register operand '") +
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printImplicitRegisterFlag(ImplicitOperands[I]) + " %" +
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getRegisterName(TRI, ImplicitOperands[I].getReg()) + "'");
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}
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return false;
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}
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bool MIParser::parseInstruction(unsigned &OpCode) {
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if (Token.isNot(MIToken::Identifier))
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return error("expected a machine instruction");
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StringRef InstrName = Token.stringValue();
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if (parseInstrName(InstrName, OpCode))
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return error(Twine("unknown machine instruction name '") + InstrName + "'");
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lex();
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return false;
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}
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bool MIParser::parseRegister(unsigned &Reg) {
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switch (Token.kind()) {
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case MIToken::underscore:
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Reg = 0;
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break;
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case MIToken::NamedRegister: {
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StringRef Name = Token.stringValue();
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if (getRegisterByName(Name, Reg))
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return error(Twine("unknown register name '") + Name + "'");
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break;
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}
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case MIToken::VirtualRegister: {
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unsigned ID;
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if (getUnsigned(ID))
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return true;
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const auto RegInfo = PFS.VirtualRegisterSlots.find(ID);
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if (RegInfo == PFS.VirtualRegisterSlots.end())
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return error(Twine("use of undefined virtual register '%") + Twine(ID) +
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"'");
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Reg = RegInfo->second;
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break;
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}
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// TODO: Parse other register kinds.
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default:
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llvm_unreachable("The current token should be a register");
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}
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return false;
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}
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bool MIParser::parseRegisterFlag(unsigned &Flags) {
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switch (Token.kind()) {
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case MIToken::kw_implicit:
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Flags |= RegState::Implicit;
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break;
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case MIToken::kw_implicit_define:
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Flags |= RegState::ImplicitDefine;
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break;
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case MIToken::kw_dead:
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Flags |= RegState::Dead;
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break;
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case MIToken::kw_killed:
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Flags |= RegState::Kill;
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break;
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case MIToken::kw_undef:
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Flags |= RegState::Undef;
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break;
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// TODO: report an error when we specify the same flag more than once.
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// TODO: parse the other register flags.
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default:
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llvm_unreachable("The current token should be a register flag");
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}
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lex();
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return false;
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}
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bool MIParser::parseSubRegisterIndex(unsigned &SubReg) {
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assert(Token.is(MIToken::colon));
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lex();
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if (Token.isNot(MIToken::Identifier))
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return error("expected a subregister index after ':'");
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auto Name = Token.stringValue();
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SubReg = getSubRegIndex(Name);
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if (!SubReg)
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return error(Twine("use of unknown subregister index '") + Name + "'");
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lex();
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return false;
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}
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bool MIParser::parseRegisterOperand(MachineOperand &Dest, bool IsDef) {
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unsigned Reg;
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unsigned Flags = IsDef ? RegState::Define : 0;
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while (Token.isRegisterFlag()) {
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if (parseRegisterFlag(Flags))
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return true;
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}
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if (!Token.isRegister())
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return error("expected a register after register flags");
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if (parseRegister(Reg))
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return true;
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lex();
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unsigned SubReg = 0;
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if (Token.is(MIToken::colon)) {
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if (parseSubRegisterIndex(SubReg))
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return true;
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}
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Dest = MachineOperand::CreateReg(
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Reg, Flags & RegState::Define, Flags & RegState::Implicit,
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Flags & RegState::Kill, Flags & RegState::Dead, Flags & RegState::Undef,
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/*isEarlyClobber=*/false, SubReg);
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return false;
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}
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bool MIParser::parseImmediateOperand(MachineOperand &Dest) {
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assert(Token.is(MIToken::IntegerLiteral));
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const APSInt &Int = Token.integerValue();
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if (Int.getMinSignedBits() > 64)
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// TODO: Replace this with an error when we can parse CIMM Machine Operands.
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llvm_unreachable("Can't parse large integer literals yet!");
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Dest = MachineOperand::CreateImm(Int.getExtValue());
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lex();
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return false;
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}
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bool MIParser::getUnsigned(unsigned &Result) {
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assert(Token.hasIntegerValue() && "Expected a token with an integer value");
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const uint64_t Limit = uint64_t(std::numeric_limits<unsigned>::max()) + 1;
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uint64_t Val64 = Token.integerValue().getLimitedValue(Limit);
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if (Val64 == Limit)
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return error("expected 32-bit integer (too large)");
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Result = Val64;
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return false;
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}
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bool MIParser::parseMBBReference(MachineBasicBlock *&MBB) {
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assert(Token.is(MIToken::MachineBasicBlock));
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unsigned Number;
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if (getUnsigned(Number))
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return true;
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auto MBBInfo = PFS.MBBSlots.find(Number);
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if (MBBInfo == PFS.MBBSlots.end())
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return error(Twine("use of undefined machine basic block #") +
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Twine(Number));
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MBB = MBBInfo->second;
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if (!Token.stringValue().empty() && Token.stringValue() != MBB->getName())
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return error(Twine("the name of machine basic block #") + Twine(Number) +
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" isn't '" + Token.stringValue() + "'");
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return false;
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}
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bool MIParser::parseMBBOperand(MachineOperand &Dest) {
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MachineBasicBlock *MBB;
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if (parseMBBReference(MBB))
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return true;
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Dest = MachineOperand::CreateMBB(MBB);
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lex();
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return false;
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}
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bool MIParser::parseGlobalAddressOperand(MachineOperand &Dest) {
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switch (Token.kind()) {
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case MIToken::NamedGlobalValue: {
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auto Name = Token.stringValue();
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const Module *M = MF.getFunction()->getParent();
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if (const auto *GV = M->getNamedValue(Name)) {
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Dest = MachineOperand::CreateGA(GV, /*Offset=*/0);
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break;
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}
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return error(Twine("use of undefined global value '@") + Name + "'");
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}
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case MIToken::GlobalValue: {
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unsigned GVIdx;
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if (getUnsigned(GVIdx))
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return true;
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if (GVIdx >= IRSlots.GlobalValues.size())
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return error(Twine("use of undefined global value '@") + Twine(GVIdx) +
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"'");
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Dest = MachineOperand::CreateGA(IRSlots.GlobalValues[GVIdx],
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/*Offset=*/0);
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break;
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}
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default:
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llvm_unreachable("The current token should be a global value");
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}
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// TODO: Parse offset and target flags.
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lex();
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return false;
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}
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bool MIParser::parseMachineOperand(MachineOperand &Dest) {
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switch (Token.kind()) {
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case MIToken::kw_implicit:
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case MIToken::kw_implicit_define:
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case MIToken::kw_dead:
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case MIToken::kw_killed:
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case MIToken::kw_undef:
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case MIToken::underscore:
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case MIToken::NamedRegister:
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case MIToken::VirtualRegister:
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return parseRegisterOperand(Dest);
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case MIToken::IntegerLiteral:
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return parseImmediateOperand(Dest);
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case MIToken::MachineBasicBlock:
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return parseMBBOperand(Dest);
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case MIToken::GlobalValue:
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case MIToken::NamedGlobalValue:
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return parseGlobalAddressOperand(Dest);
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case MIToken::Error:
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return true;
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case MIToken::Identifier:
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if (const auto *RegMask = getRegMask(Token.stringValue())) {
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Dest = MachineOperand::CreateRegMask(RegMask);
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lex();
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break;
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}
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// fallthrough
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default:
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// TODO: parse the other machine operands.
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return error("expected a machine operand");
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}
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return false;
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}
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void MIParser::initNames2InstrOpCodes() {
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if (!Names2InstrOpCodes.empty())
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return;
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const auto *TII = MF.getSubtarget().getInstrInfo();
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assert(TII && "Expected target instruction info");
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for (unsigned I = 0, E = TII->getNumOpcodes(); I < E; ++I)
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Names2InstrOpCodes.insert(std::make_pair(StringRef(TII->getName(I)), I));
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|
}
|
|
|
|
bool MIParser::parseInstrName(StringRef InstrName, unsigned &OpCode) {
|
|
initNames2InstrOpCodes();
|
|
auto InstrInfo = Names2InstrOpCodes.find(InstrName);
|
|
if (InstrInfo == Names2InstrOpCodes.end())
|
|
return true;
|
|
OpCode = InstrInfo->getValue();
|
|
return false;
|
|
}
|
|
|
|
void MIParser::initNames2Regs() {
|
|
if (!Names2Regs.empty())
|
|
return;
|
|
// The '%noreg' register is the register 0.
|
|
Names2Regs.insert(std::make_pair("noreg", 0));
|
|
const auto *TRI = MF.getSubtarget().getRegisterInfo();
|
|
assert(TRI && "Expected target register info");
|
|
for (unsigned I = 0, E = TRI->getNumRegs(); I < E; ++I) {
|
|
bool WasInserted =
|
|
Names2Regs.insert(std::make_pair(StringRef(TRI->getName(I)).lower(), I))
|
|
.second;
|
|
(void)WasInserted;
|
|
assert(WasInserted && "Expected registers to be unique case-insensitively");
|
|
}
|
|
}
|
|
|
|
bool MIParser::getRegisterByName(StringRef RegName, unsigned &Reg) {
|
|
initNames2Regs();
|
|
auto RegInfo = Names2Regs.find(RegName);
|
|
if (RegInfo == Names2Regs.end())
|
|
return true;
|
|
Reg = RegInfo->getValue();
|
|
return false;
|
|
}
|
|
|
|
void MIParser::initNames2RegMasks() {
|
|
if (!Names2RegMasks.empty())
|
|
return;
|
|
const auto *TRI = MF.getSubtarget().getRegisterInfo();
|
|
assert(TRI && "Expected target register info");
|
|
ArrayRef<const uint32_t *> RegMasks = TRI->getRegMasks();
|
|
ArrayRef<const char *> RegMaskNames = TRI->getRegMaskNames();
|
|
assert(RegMasks.size() == RegMaskNames.size());
|
|
for (size_t I = 0, E = RegMasks.size(); I < E; ++I)
|
|
Names2RegMasks.insert(
|
|
std::make_pair(StringRef(RegMaskNames[I]).lower(), RegMasks[I]));
|
|
}
|
|
|
|
const uint32_t *MIParser::getRegMask(StringRef Identifier) {
|
|
initNames2RegMasks();
|
|
auto RegMaskInfo = Names2RegMasks.find(Identifier);
|
|
if (RegMaskInfo == Names2RegMasks.end())
|
|
return nullptr;
|
|
return RegMaskInfo->getValue();
|
|
}
|
|
|
|
void MIParser::initNames2SubRegIndices() {
|
|
if (!Names2SubRegIndices.empty())
|
|
return;
|
|
const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
|
|
for (unsigned I = 1, E = TRI->getNumSubRegIndices(); I < E; ++I)
|
|
Names2SubRegIndices.insert(
|
|
std::make_pair(StringRef(TRI->getSubRegIndexName(I)).lower(), I));
|
|
}
|
|
|
|
unsigned MIParser::getSubRegIndex(StringRef Name) {
|
|
initNames2SubRegIndices();
|
|
auto SubRegInfo = Names2SubRegIndices.find(Name);
|
|
if (SubRegInfo == Names2SubRegIndices.end())
|
|
return 0;
|
|
return SubRegInfo->getValue();
|
|
}
|
|
|
|
bool llvm::parseMachineInstr(MachineInstr *&MI, SourceMgr &SM,
|
|
MachineFunction &MF, StringRef Src,
|
|
const PerFunctionMIParsingState &PFS,
|
|
const SlotMapping &IRSlots, SMDiagnostic &Error) {
|
|
return MIParser(SM, MF, Error, Src, PFS, IRSlots).parse(MI);
|
|
}
|
|
|
|
bool llvm::parseMBBReference(MachineBasicBlock *&MBB, SourceMgr &SM,
|
|
MachineFunction &MF, StringRef Src,
|
|
const PerFunctionMIParsingState &PFS,
|
|
const SlotMapping &IRSlots, SMDiagnostic &Error) {
|
|
return MIParser(SM, MF, Error, Src, PFS, IRSlots).parseMBB(MBB);
|
|
}
|