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c9978bab4b
Disallow all mutation of `MCSubtargetInfo` expect the feature bits. Besides deleting the assignment operators -- which were dead "code" -- this restricts `InitMCProcessorInfo()` to subclass initialization sequences, and exposes a new more limited function called `setDefaultFeatures()` for use by the ARMAsmParser `.cpu` directive. There's a small functional change here: ARMAsmParser used to adjust `MCSubtargetInfo::CPUSchedModel` as a side effect of calling `InitMCProcessorInfo()`, but I've removed that suspicious behaviour. Since the AsmParser shouldn't be doing any scheduling, there shouldn't be any observable change... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241961 91177308-0d34-0410-b5e6-96231b3b80d8
113 lines
4.1 KiB
C++
113 lines
4.1 KiB
C++
//===-- MCSubtargetInfo.cpp - Subtarget Information -----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/MC/MCInstrItineraries.h"
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#include "llvm/MC/SubtargetFeature.h"
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#include "llvm/Support/raw_ostream.h"
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#include <algorithm>
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using namespace llvm;
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static FeatureBitset getFeatures(StringRef CPU, StringRef FS,
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ArrayRef<SubtargetFeatureKV> ProcDesc,
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ArrayRef<SubtargetFeatureKV> ProcFeatures) {
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SubtargetFeatures Features(FS);
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return Features.getFeatureBits(CPU, ProcDesc, ProcFeatures);
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}
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void MCSubtargetInfo::InitMCProcessorInfo(StringRef CPU, StringRef FS) {
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FeatureBits = getFeatures(CPU, FS, ProcDesc, ProcFeatures);
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if (!CPU.empty())
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CPUSchedModel = &getSchedModelForCPU(CPU);
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else
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CPUSchedModel = &MCSchedModel::GetDefaultSchedModel();
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}
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void MCSubtargetInfo::setDefaultFeatures(StringRef CPU) {
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FeatureBits = getFeatures(CPU, "", ProcDesc, ProcFeatures);
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}
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MCSubtargetInfo::MCSubtargetInfo(
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const Triple &TT, StringRef C, StringRef FS,
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ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PD,
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const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR,
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const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
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const InstrStage *IS, const unsigned *OC, const unsigned *FP)
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: TargetTriple(TT), CPU(C), ProcFeatures(PF), ProcDesc(PD),
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ProcSchedModels(ProcSched), WriteProcResTable(WPR), WriteLatencyTable(WL),
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ReadAdvanceTable(RA), Stages(IS), OperandCycles(OC), ForwardingPaths(FP) {
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InitMCProcessorInfo(CPU, FS);
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}
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/// ToggleFeature - Toggle a feature and returns the re-computed feature
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/// bits. This version does not change the implied bits.
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FeatureBitset MCSubtargetInfo::ToggleFeature(uint64_t FB) {
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FeatureBits.flip(FB);
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return FeatureBits;
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}
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FeatureBitset MCSubtargetInfo::ToggleFeature(const FeatureBitset &FB) {
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FeatureBits ^= FB;
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return FeatureBits;
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}
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/// ToggleFeature - Toggle a feature and returns the re-computed feature
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/// bits. This version will also change all implied bits.
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FeatureBitset MCSubtargetInfo::ToggleFeature(StringRef FS) {
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SubtargetFeatures Features;
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FeatureBits = Features.ToggleFeature(FeatureBits, FS, ProcFeatures);
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return FeatureBits;
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}
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FeatureBitset MCSubtargetInfo::ApplyFeatureFlag(StringRef FS) {
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SubtargetFeatures Features;
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FeatureBits = Features.ApplyFeatureFlag(FeatureBits, FS, ProcFeatures);
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return FeatureBits;
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}
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const MCSchedModel &MCSubtargetInfo::getSchedModelForCPU(StringRef CPU) const {
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assert(ProcSchedModels && "Processor machine model not available!");
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unsigned NumProcs = ProcDesc.size();
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#ifndef NDEBUG
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for (size_t i = 1; i < NumProcs; i++) {
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assert(strcmp(ProcSchedModels[i - 1].Key, ProcSchedModels[i].Key) < 0 &&
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"Processor machine model table is not sorted");
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}
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#endif
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// Find entry
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const SubtargetInfoKV *Found =
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std::lower_bound(ProcSchedModels, ProcSchedModels+NumProcs, CPU);
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if (Found == ProcSchedModels+NumProcs || StringRef(Found->Key) != CPU) {
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if (CPU != "help") // Don't error if the user asked for help.
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errs() << "'" << CPU
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<< "' is not a recognized processor for this target"
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<< " (ignoring processor)\n";
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return MCSchedModel::GetDefaultSchedModel();
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}
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assert(Found->Value && "Missing processor SchedModel value");
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return *(const MCSchedModel *)Found->Value;
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}
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InstrItineraryData
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MCSubtargetInfo::getInstrItineraryForCPU(StringRef CPU) const {
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const MCSchedModel SchedModel = getSchedModelForCPU(CPU);
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return InstrItineraryData(SchedModel, Stages, OperandCycles, ForwardingPaths);
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}
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/// Initialize an InstrItineraryData instance.
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void MCSubtargetInfo::initInstrItins(InstrItineraryData &InstrItins) const {
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InstrItins = InstrItineraryData(getSchedModel(), Stages, OperandCycles,
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ForwardingPaths);
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}
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