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https://github.com/c64scene-ar/llvm-6502.git
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4e703f82f2
On PPC64, we end up with lots of i32 -> i64 zero extensions, not only from all of the usual places, but also from the ABI, which specifies that values passed are zero extended. Almost all 32-bit PPC instructions in PPC64 mode are defined to do *something* to the higher-order bits, and for some instructions, that action clears those bits (thus providing a zero-extended result). This is especially common after rotate-and-mask instructions. Adding an additional instruction to zero-extend the results of these instructions is unnecessary. This PPCISelDAGToDAG peephole optimization examines these zero-extensions, and looks back through their operands to see if all instructions will implicitly zero extend their results. If so, we convert these instructions to their 64-bit variants (which is an internal change only, the actual encoding of these instructions is the same as the original 32-bit ones) and remove the unnecessary zero-extension (changing where the INSERT_SUBREG instructions are to make everything internally consistent). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224169 91177308-0d34-0410-b5e6-96231b3b80d8
33 lines
689 B
LLVM
33 lines
689 B
LLVM
; RUN: llc -mcpu=pwr7 < %s | FileCheck %s
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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; Function Attrs: nounwind readnone
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define signext i32 @foo(i32 signext %a) #0 {
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entry:
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%mul = mul nsw i32 %a, %a
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%shr2 = lshr i32 %mul, 5
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ret i32 %shr2
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; CHECK-LABEL @foo
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; CHECK-NOT: rldicl 3, {{[0-9]+}}, 0, 32
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; CHECK: blr
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}
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define zeroext i32 @test6(i32 zeroext %x) #0 {
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entry:
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%and = lshr i32 %x, 16
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%shr = and i32 %and, 255
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%and1 = shl i32 %x, 16
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%shl = and i32 %and1, 16711680
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%or = or i32 %shr, %shl
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ret i32 %or
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; CHECK-LABEL @test6
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; CHECK-NOT: rldicl 3, {{[0-9]+}}, 0, 32
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; CHECK: blr
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}
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attributes #0 = { nounwind readnone }
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