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https://github.com/c64scene-ar/llvm-6502.git
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ceb9150268
Summary: I don't know why every singled backend had to redeclare its own DataLayout. There was a virtual getDataLayout() on the common base TargetMachine, the default implementation returned nullptr. It was not clear from this that we could assume at call site that a DataLayout will be available with each Target. Now getDataLayout() is no longer virtual and return a pointer to the DataLayout member of the common base TargetMachine. I plan to turn it into a reference in a future patch. The only backend that didn't have a DataLayout previsouly was the CPPBackend. It now initializes the default DataLayout. This commit is NFC for all the other backends. Test Plan: clang+llvm ninja check-all Reviewers: echristo Subscribers: jfb, jholewinski, llvm-commits Differential Revision: http://reviews.llvm.org/D8243 From: Mehdi Amini <mehdi.amini@apple.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231987 91177308-0d34-0410-b5e6-96231b3b80d8
128 lines
4.1 KiB
C++
128 lines
4.1 KiB
C++
//===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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#include "SparcTargetMachine.h"
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#include "SparcTargetObjectFile.h"
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#include "Sparc.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/IR/LegacyPassManager.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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extern "C" void LLVMInitializeSparcTarget() {
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// Register the target.
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RegisterTargetMachine<SparcV8TargetMachine> X(TheSparcTarget);
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RegisterTargetMachine<SparcV9TargetMachine> Y(TheSparcV9Target);
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}
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static std::string computeDataLayout(bool is64Bit) {
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// Sparc is big endian.
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std::string Ret = "E-m:e";
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// Some ABIs have 32bit pointers.
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if (!is64Bit)
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Ret += "-p:32:32";
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// Alignments for 64 bit integers.
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Ret += "-i64:64";
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// On SparcV9 128 floats are aligned to 128 bits, on others only to 64.
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// On SparcV9 registers can hold 64 or 32 bits, on others only 32.
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if (is64Bit)
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Ret += "-n32:64";
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else
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Ret += "-f128:64-n32";
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if (is64Bit)
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Ret += "-S128";
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else
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Ret += "-S64";
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return Ret;
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}
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/// SparcTargetMachine ctor - Create an ILP32 architecture model
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///
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SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL, bool is64bit)
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: LLVMTargetMachine(T, computeDataLayout(is64bit), TT, CPU, FS, Options, RM,
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CM, OL),
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TLOF(make_unique<SparcELFTargetObjectFile>()),
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Subtarget(TT, CPU, FS, *this, is64bit) {
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initAsmInfo();
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}
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SparcTargetMachine::~SparcTargetMachine() {}
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namespace {
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/// Sparc Code Generator Pass Configuration Options.
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class SparcPassConfig : public TargetPassConfig {
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public:
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SparcPassConfig(SparcTargetMachine *TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {}
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SparcTargetMachine &getSparcTargetMachine() const {
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return getTM<SparcTargetMachine>();
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}
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void addIRPasses() override;
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bool addInstSelector() override;
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void addPreEmitPass() override;
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};
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} // namespace
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TargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM) {
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return new SparcPassConfig(this, PM);
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}
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void SparcPassConfig::addIRPasses() {
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addPass(createAtomicExpandPass(&getSparcTargetMachine()));
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TargetPassConfig::addIRPasses();
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}
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bool SparcPassConfig::addInstSelector() {
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addPass(createSparcISelDag(getSparcTargetMachine()));
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return false;
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}
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void SparcPassConfig::addPreEmitPass(){
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addPass(createSparcDelaySlotFillerPass(getSparcTargetMachine()));
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}
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void SparcV8TargetMachine::anchor() { }
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SparcV8TargetMachine::SparcV8TargetMachine(const Target &T,
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StringRef TT, StringRef CPU,
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StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM,
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CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
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}
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void SparcV9TargetMachine::anchor() { }
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SparcV9TargetMachine::SparcV9TargetMachine(const Target &T,
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StringRef TT, StringRef CPU,
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StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM,
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CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
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}
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