Andrew Trick 6606ef0e98 MI-Sched: Model "reserved" processor resources. ... This allows a target to use MI-Sched as an in-order scheduler that will model strict resource conflicts without defining a processor itinerary. Instead, the target can now use the new per-operand machine model and define in-order resources with BufferSize=0. For example, this would allow restricting the type of operations that can be formed into a dispatch group. (Normally NumMicroOps is sufficient to enforce dispatch groups). If the intent is to model latency in in-order pipeline, as opposed to resource conflicts, then a resource with BufferSize=1 should be defined instead. This feature is only casually tested as there are no in-tree targets using it yet. However, Hal will be experimenting with POWER7. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196517 91177308-0d34-0410-b5e6-96231b3b80d8		2013-12-05 17:56:02 +00:00
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ADT	Correct word hyphenations	2013-12-05 05:44:44 +00:00
Analysis	Correct word hyphenations	2013-12-05 05:44:44 +00:00
Assembly
Bitcode
CodeGen	MI-Sched: Model "reserved" processor resources.	2013-12-05 17:56:02 +00:00
Config
DebugInfo
ExecutionEngine
IR	Use present fast-math flags when applicable in CreateBinOp	2013-12-05 00:32:09 +00:00
IRReader
LTO
MC	Machine model comments. Explain a ProcessorUnit's BufferSize.	2013-12-05 17:55:53 +00:00
Object
Option
Support	Correct word hyphenations	2013-12-05 05:44:44 +00:00
TableGen
Target	Machine model comments. Explain a ProcessorUnit's BufferSize.	2013-12-05 17:55:53 +00:00
Transforms	Add forgotten header guards	2013-12-05 12:52:32 +00:00
AutoUpgrade.h
CMakeLists.txt
DebugInfo.h
DIBuilder.h
GVMaterializer.h
InitializePasses.h
InstVisitor.h
LinkAllIR.h
LinkAllPasses.h
Linker.h
Pass.h
PassAnalysisSupport.h
PassManager.h
PassRegistry.h
PassSupport.h