mirror of
https://github.com/c64scene-ar/llvm-6502.git
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a65ca9dcf0
Extend what's currently done for shift because the HW performs this masking implicitly: (rotl:i32 x, (and y, 31)) -> (rotl:i32 x, y) I use the newly factored out multiclass that was only supporting shifts so far. For testing I extended my testcase for the new rotation idiom. <rdar://problem/15295856> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203718 91177308-0d34-0410-b5e6-96231b3b80d8
135 lines
2.8 KiB
LLVM
135 lines
2.8 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=generic | FileCheck %s
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; Check that we recognize this idiom for rotation too:
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; a << (b & (OpSize-1)) | a >> ((0 - b) & (OpSize-1))
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define i32 @rotate_left_32(i32 %a, i32 %b) {
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; CHECK-LABEL: rotate_left_32:
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; CHECK-NOT: and
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; CHECK: roll
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entry:
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%and = and i32 %b, 31
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%shl = shl i32 %a, %and
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%0 = sub i32 0, %b
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%and3 = and i32 %0, 31
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%shr = lshr i32 %a, %and3
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%or = or i32 %shl, %shr
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ret i32 %or
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}
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define i32 @rotate_right_32(i32 %a, i32 %b) {
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; CHECK-LABEL: rotate_right_32:
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; CHECK-NOT: and
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; CHECK: rorl
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entry:
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%and = and i32 %b, 31
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%shl = lshr i32 %a, %and
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%0 = sub i32 0, %b
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%and3 = and i32 %0, 31
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%shr = shl i32 %a, %and3
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%or = or i32 %shl, %shr
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ret i32 %or
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}
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define i64 @rotate_left_64(i64 %a, i64 %b) {
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; CHECK-LABEL: rotate_left_64:
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; CHECK-NOT: and
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; CHECK: rolq
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entry:
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%and = and i64 %b, 63
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%shl = shl i64 %a, %and
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%0 = sub i64 0, %b
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%and3 = and i64 %0, 63
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%shr = lshr i64 %a, %and3
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%or = or i64 %shl, %shr
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ret i64 %or
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}
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define i64 @rotate_right_64(i64 %a, i64 %b) {
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; CHECK-LABEL: rotate_right_64:
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; CHECK-NOT: and
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; CHECK: rorq
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entry:
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%and = and i64 %b, 63
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%shl = lshr i64 %a, %and
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%0 = sub i64 0, %b
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%and3 = and i64 %0, 63
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%shr = shl i64 %a, %and3
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%or = or i64 %shl, %shr
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ret i64 %or
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}
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; Also check mem operand.
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define void @rotate_left_m32(i32 *%pa, i32 %b) {
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; CHECK-LABEL: rotate_left_m32:
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; CHECK-NOT: and
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; CHECK: roll
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; no store:
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; CHECK-NOT: mov
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entry:
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%a = load i32* %pa, align 16
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%and = and i32 %b, 31
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%shl = shl i32 %a, %and
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%0 = sub i32 0, %b
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%and3 = and i32 %0, 31
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%shr = lshr i32 %a, %and3
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%or = or i32 %shl, %shr
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store i32 %or, i32* %pa, align 32
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ret void
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}
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define void @rotate_right_m32(i32 *%pa, i32 %b) {
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; CHECK-LABEL: rotate_right_m32:
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; CHECK-NOT: and
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; CHECK: rorl
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; no store:
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; CHECK-NOT: mov
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entry:
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%a = load i32* %pa, align 16
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%and = and i32 %b, 31
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%shl = lshr i32 %a, %and
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%0 = sub i32 0, %b
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%and3 = and i32 %0, 31
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%shr = shl i32 %a, %and3
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%or = or i32 %shl, %shr
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store i32 %or, i32* %pa, align 32
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ret void
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}
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define void @rotate_left_m64(i64 *%pa, i64 %b) {
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; CHECK-LABEL: rotate_left_m64:
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; CHECK-NOT: and
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; CHECK: rolq
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; no store:
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; CHECK-NOT: mov
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entry:
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%a = load i64* %pa, align 16
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%and = and i64 %b, 63
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%shl = shl i64 %a, %and
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%0 = sub i64 0, %b
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%and3 = and i64 %0, 63
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%shr = lshr i64 %a, %and3
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%or = or i64 %shl, %shr
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store i64 %or, i64* %pa, align 64
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ret void
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}
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define void @rotate_right_m64(i64 *%pa, i64 %b) {
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; CHECK-LABEL: rotate_right_m64:
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; CHECK-NOT: and
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; CHECK: rorq
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; no store:
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; CHECK-NOT: mov
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entry:
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%a = load i64* %pa, align 16
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%and = and i64 %b, 63
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%shl = lshr i64 %a, %and
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%0 = sub i64 0, %b
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%and3 = and i64 %0, 63
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%shr = shl i64 %a, %and3
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%or = or i64 %shl, %shr
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store i64 %or, i64* %pa, align 64
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ret void
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}
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