llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-01 02:33:44 +00:00

History

Hal Finkel eda8f6708d PPC: Optimize rldicl generation for masked shifts

Masking operations (where only some number of the low bits are being kept) are
selected to rldicl(x, 0, mb). If x is a logical right shift (which would become
rldicl(y, 64-n, n)), we might be able to fold the two instructions together:

  rldicl(rldicl(x, 64-n, n), 0, mb) -> rldicl(x, 64-n, mb) for n <= mb

The right shift is really a left rotate followed by a mask, and if the explicit
mask is a more-restrictive sub-mask of the mask implied by the shift, only one
rldicl is needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195185 91177308-0d34-0410-b5e6-96231b3b80d8

2013-11-20 01:10:15 +00:00

Analysis

Use correct size for address space in BasicAA.

2013-11-16 00:36:43 +00:00

Assembler

Make it explicit that nulls are not allowed in names.

2013-11-19 21:12:39 +00:00

Bindings

[OCaml] Add REQUIRES: native, object-emission to the Target test

2013-11-15 03:43:51 +00:00

Bitcode

The 'optnone' attribute means don't inline anything into this function