Evan Cheng 5248468473 Enable cross register class coalescing. ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76281 91177308-0d34-0410-b5e6-96231b3b80d8

2009-07-18 02:10:10 +00:00

..

Alpha

Make promotion in operation legalization for SETCC work correctly.

2009-07-17 05:16:04 +00:00

ARM

fix an arm codegen bug (the same as PR4482 on ppc) where available_externally

2009-07-15 04:12:33 +00:00

CBackend

Fix an erroneous check for isFNeg; the FNeg case is handled

2009-06-04 23:43:29 +00:00

CellSPU

Add some generic expansion logic for SMULO and UMULO. Fixes UMULO

2009-06-16 06:58:29 +00:00

CPP

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Generic

remove tests for removed intrinsics.

2009-07-12 21:30:06 +00:00

IA64

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Mips

Split the Add, Sub, and Mul instruction opcodes into separate

2009-06-04 22:49:04 +00:00

MSP430

Split the Add, Sub, and Mul instruction opcodes into separate

2009-06-04 22:49:04 +00:00

PowerPC

Teach MachineInstr::isRegTiedToDefOperand() to correctly parse inline asm operands.

2009-07-16 20:58:34 +00:00

SPARC

Split the Add, Sub, and Mul instruction opcodes into separate

2009-06-04 22:49:04 +00:00

SystemZ

Enable cross register class coalescing.

2009-07-18 02:10:10 +00:00

Thumb

Smarter isel of ldrsb / ldrsh. Only make use of these when [r,r] address is feasible.

2009-07-11 07:08:13 +00:00

Thumb2

Emit cross regclass register moves for thumb2.

2009-07-16 23:26:06 +00:00

X86

Enable cross register class coalescing.

2009-07-18 02:10:10 +00:00

XCore

Combine an unaligned store of unaligned load into a memmove.

2009-07-16 12:50:48 +00:00