Elena Demikhovsky 52a35a89e6 I added several lines in X86 code generator that allow to choose ...

VSHUFPS/VSHUFPD instructions while lowering VECTOR_SHUFFLE node. I check a commuted VSHUFP mask.

The patch was reviewed by Bruno.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145099 91177308-0d34-0410-b5e6-96231b3b80d8

2011-11-23 10:23:16 +00:00

..

ARM

When fast iseling a GEP, accumulate the offset rather than emitting a series of

2011-11-17 07:15:58 +00:00

CBackend

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CellSPU

Remove histogram tests.

2011-11-12 22:39:40 +00:00

CPP

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Generic

Remove the the test which checks the saving of a vector of booleans into memory.

2011-10-16 19:06:06 +00:00

MBlaze

Change the default scheduler from Latency to ILP, since Latency

2011-10-24 17:45:02 +00:00

Mips

Reapply r143206, with fixes. Disallow physical register lifetimes

2011-11-03 21:49:52 +00:00

MSP430

Remove the explicit request for "Latency" scheduling from MSP430,

2011-10-24 17:53:16 +00:00

PowerPC

add basic PPC register-pressure feedback; adjust the vaarg test to match the new register-allocation pattern

2011-11-22 16:21:04 +00:00

PTX

allow non-device function calls in PTX when natively handling device-side printf

2011-11-11 14:45:12 +00:00

SPARC

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Thumb

Reapply r143206, with fixes. Disallow physical register lifetimes

2011-11-03 21:49:52 +00:00

Thumb2

Add vmov.f32 to materialize f32 immediate splats which cannot be handled by

2011-11-15 02:12:34 +00:00

X86

I added several lines in X86 code generator that allow to choose

2011-11-23 10:23:16 +00:00

XCore

Don't fold negative offsets into cp / dp accesses to avoid relocation errors.

2011-11-01 11:31:53 +00:00