Craig Topper 82a644adf2 Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of 0xa6/0xa7, and adding MRM_C0/MRM_E0 forms. Removes 376K from the disassembler tables. ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201641 91177308-0d34-0410-b5e6-96231b3b80d8

2014-02-19 05:34:21 +00:00

..

AArch64

[AArch64 NEON]Fix a assertion failure when disassemble SHLL instruction.

2013-11-29 01:29:16 +00:00

ARM

ARM: change implicit immediate forms of {ld,st}r{,b}t to psuedo-instructions

2014-01-12 04:36:01 +00:00

Mips

LL and SC decoder method fix.

2014-01-15 13:17:33 +00:00

PowerPC

Add a disassembler to the PowerPC backend

2013-12-19 16:13:01 +00:00

Sparc

[Sparc] Correct quad register list in the asm parser.

2014-01-24 05:24:01 +00:00

SystemZ

[SystemZ] Add MC support for interlocked-access 1 instructions

2013-12-24 15:14:05 +00:00

X86

Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of 0xa6/0xa7, and adding MRM_C0/MRM_E0 forms. Removes 376K from the disassembler tables.

2014-02-19 05:34:21 +00:00

XCore

[tests] Cleanup initialization of test suffixes.

2013-08-16 00:37:11 +00:00