Jim Laskey 538421411a Added InstrSchedClass to each of the PowerPC Instructions. ...

Note that when adding new instructions that you should refer to the table at the
bottom of PPCSchedule.td.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23830 91177308-0d34-0410-b5e6-96231b3b80d8

2005-10-19 19:51:16 +00:00

..

Alpha

This seems useful from the original patch that added the function. If there is a reason it is not useful on a RISC type target, let me know and I will pull it out

2005-10-09 20:11:35 +00:00

CBackend

fix CBackend/2005-09-27-VolatileFuncPtr.ll

2005-09-27 20:52:44 +00:00

IA64

Fix CodeGen/Generic/bool-to-double.ll

2005-10-07 04:50:48 +00:00

PowerPC

Added InstrSchedClass to each of the PowerPC Instructions.

2005-10-19 19:51:16 +00:00

Skeleton

CR registers are not used by this "target"

2005-09-30 06:43:58 +00:00

Sparc

silence some warnings

2005-10-05 17:15:09 +00:00

SparcV8

silence some warnings

2005-10-05 17:15:09 +00:00

SparcV9

silence a warning

2005-10-02 16:27:59 +00:00

X86

Remove some dead code now that the dag combiner exists.

2005-10-15 22:08:02 +00:00

Makefile

…

MRegisterInfo.cpp

Rename MRegisterDesc -> TargetRegisterDesc for consistency

2005-09-30 17:49:27 +00:00

SubtargetFeature.cpp

Print:

2005-09-07 05:44:14 +00:00

Target.td

Added InstrSchedClass to each of the PowerPC Instructions.

2005-10-19 19:51:16 +00:00

TargetData.cpp

…

TargetFrameInfo.cpp

…

TargetInstrInfo.cpp

…

TargetMachine.cpp

…

TargetMachineRegistry.cpp

1. Use SubtargetFeatures in llc/lli.

2005-09-01 21:38:21 +00:00

TargetSchedInfo.cpp

…

TargetSchedule.td

Push processor descriptions to the top of target and add command line info.

2005-10-19 13:34:52 +00:00

TargetSelectionDAG.td

add the integer truncate/extension operations

2005-10-14 06:40:20 +00:00

TargetSubtarget.cpp

…