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LLVM backend for 6502
54cfeda745
The old code would look at kills and defs in one pass over the instruction operands, causing problems with this code: %R0<def>, %CPSR<def,dead> = tLSLri %R5<kill>, 2, pred:14, pred:%noreg %R0<def>, %CPSR<def,dead> = tADDrr %R4<kill>, %R0<kill>, pred:14, %pred:%noreg The last instruction kills and redefines %R0, so it is still live after the instruction. This caused a register scavenger crash when compiling 483.xalancbmk for armv6. I am not including a test case because it requires too much bad luck to expose this old bug. First you need to convince the register allocator to use %R0 twice on the tADDrr instruction, then you have to convince BranchFolding to do something that causes it to run the register scavenger on he bad block. <rdar://problem/9898200> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136973 91177308-0d34-0410-b5e6-96231b3b80d8 |
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