Vincent Lejeune 8e37705a73 R600: Avoid more than 4 literals in the same instruction group at scheduling ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187515 91177308-0d34-0410-b5e6-96231b3b80d8		2013-07-31 19:32:07 +00:00
..
AArch64
ARM	This test may have been sensitive to the ARM ABI...	2013-07-30 20:34:59 +00:00
CPP
Generic
Hexagon
Inputs
Mips
MSP430
NVPTX
PowerPC
R600	R600: Avoid more than 4 literals in the same instruction group at scheduling	2013-07-31 19:32:07 +00:00
SI
SPARC
SystemZ	[SystemZ] Implement isLegalAddressingMode()	2013-07-31 12:58:26 +00:00
Thumb	Debug Info: update testing cases to pass verifier.	2013-07-29 18:12:58 +00:00
Thumb2
X86	Added INSERT and EXTRACT intructions from AVX-512 ISA.	2013-07-31 11:35:14 +00:00
XCore