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https://github.com/c64scene-ar/llvm-6502.git
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11ba3b1af6
subreg form on x86-64, to avoid the problem with x86-32 having GPRs that don't have 8-bit subregs. Also, change several 16-bit instructions to use equivalent 32-bit instructions. These have a smaller encoding and avoid partial-register updates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54223 91177308-0d34-0410-b5e6-96231b3b80d8
29 lines
760 B
LLVM
29 lines
760 B
LLVM
; RUN: llvm-as < %s | llc -march=x86-64 > %t
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; RUN: not grep and %t
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; RUN: not grep movzbq %t
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; RUN: not grep movzwq %t
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; RUN: not grep movzlq %t
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; These should use movzbl instead of 'and 255'.
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; This related to not having a ZERO_EXTEND_REG opcode.
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; This test was split out of zext-inreg-0.ll because these
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; cases don't yet work on x86-32 due to the 8-bit subreg
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; issue.
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define i32 @a(i32 %d) nounwind {
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%e = add i32 %d, 1
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%retval = and i32 %e, 255
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ret i32 %retval
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}
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define i32 @b(float %d) nounwind {
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%tmp12 = fptoui float %d to i8
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%retval = zext i8 %tmp12 to i32
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ret i32 %retval
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}
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define i64 @d(i64 %d) nounwind {
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%e = add i64 %d, 1
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%retval = and i64 %e, 255
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ret i64 %retval
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}
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