Louis Gerbarg 5540570374 Improve ARM64 vector creation
This patch improves the performance of vector creation in caseiswhere where
several of the lanes in the vector are a constant floating point value. It
also includes new patterns to fold together some of the instructions when the
value is 0.0f. Test cases included.

rdar://16349427

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206496 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-17 20:51:50 +00:00
..
2014-04-17 19:14:06 +00:00
2014-04-17 20:51:50 +00:00