Richard Barton c8f2fcc9a3 Correct decoder for T1 conditional B encoding ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158055 91177308-0d34-0410-b5e6-96231b3b80d8

2012-06-06 09:12:53 +00:00

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arm-tests.txt

Specify cpu to unbreak tests.

2012-04-26 01:38:10 +00:00

basic-arm-instructions.txt

Specify cpu to unbreak tests.

2012-04-26 01:38:10 +00:00

fp-encoding.txt

Fixed disassembler for vstm/vldm ARM VFP instructions.

2012-05-03 16:38:40 +00:00

invalid-Bcc-thumb.txt

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invalid-BFI-arm.txt

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invalid-CPS2p-arm.txt

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invalid-CPS3p-arm.txt

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invalid-DMB-thumb.txt

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invalid-DSB-arm.txt

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invalid-IT-CBNZ-thumb.txt

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invalid-IT-CC15.txt

Change ARMInstPrinter::printPredicateOperand() so it will not abort if it

2012-03-01 22:13:02 +00:00

invalid-IT-thumb.txt

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invalid-LDC-form-arm.txt

Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter.

2011-08-09 20:55:18 +00:00

invalid-LDM-thumb.txt

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invalid-LDR_POST-arm.txt

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invalid-LDR_PRE-arm.txt

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invalid-LDRB_POST-arm.txt

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invalid-LDRD_PRE-thumb.txt

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invalid-LDRrs-arm.txt

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invalid-MCR-arm.txt

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invalid-MOVr-arm.txt

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invalid-MOVs-arm.txt

Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter.

2011-08-09 20:55:18 +00:00

invalid-MOVs-LSL-arm.txt

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invalid-MOVTi16-arm.txt

Push GPRnopc through a large number of instruction definitions to tighten operand decoding.

2011-08-10 00:03:03 +00:00

invalid-MRRC2-arm.txt

Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the disassembler. Since the upredicability conditions are complex, C++ code was added to handle them.

2012-04-18 13:12:50 +00:00

invalid-MSRi-arm.txt

Continue to tighten decoding by performing more operand validation.

2011-08-11 20:21:46 +00:00

invalid-RFEorLDMIA-arm.txt

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invalid-SBFX-arm.txt

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invalid-SMLAD-arm.txt

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invalid-SRS-arm.txt

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invalid-STMIA_UPD-thumb.txt

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invalid-SXTB-arm.txt

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invalid-t2Bcc-thumb.txt

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invalid-t2LDRBT-thumb.txt

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invalid-t2LDREXD-thumb.txt

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invalid-t2LDRSHi8-thumb.txt

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invalid-t2LDRSHi12-thumb.txt

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invalid-t2PUSH-thumb.txt

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invalid-t2STR_POST-thumb.txt

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invalid-t2STRD_PRE-thumb.txt

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invalid-t2STREXB-thumb.txt

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invalid-t2STREXD-thumb.txt

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invalid-UMAAL-arm.txt

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invalid-VLD1DUPq8_UPD-arm.txt

Specify cpu to unbreak tests.

2012-04-26 01:38:10 +00:00

invalid-VLD3DUPd32_UPD-thumb.txt

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invalid-VLDMSDB_UPD-arm.txt

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invalid-VQADD-arm.txt

Specify cpu to unbreak tests.

2012-04-26 01:38:10 +00:00

invalid-VST1d8Twb_register-thumb.txt

Fixed a case of ARM disassembly getting an assert on a bad encoding

2012-04-11 22:40:17 +00:00

invalid-VST2b32_UPD-arm.txt

Specify cpu to unbreak tests.

2012-04-26 01:38:10 +00:00

ldrd-armv4.txt

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lit.local.cfg

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memory-arm-instructions.txt

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neon-tests.txt

Specify cpu to unbreak tests.

2012-04-26 01:38:10 +00:00

neon.txt

Specify cpu to unbreak tests.

2012-04-26 01:38:10 +00:00

neont2.txt

Specify cpu to unbreak tests.

2012-04-26 01:38:10 +00:00

thumb1.txt

Correct decoder for T1 conditional B encoding

2012-06-06 09:12:53 +00:00

thumb2.txt

Specify cpu to unbreak tests.

2012-04-26 01:38:10 +00:00

thumb-MSR-MClass.txt

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thumb-printf.txt

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thumb-tests.txt

Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bits

2012-05-03 22:41:56 +00:00

unpredictable-ADC-arm.txt

Added support for unpredictable ADC/SBC instructions on ARM, and also fixed some corner cases involving the PC register as an operand for these instructions.

2012-04-05 16:19:29 +00:00

unpredictable-ADDREXT3-arm.txt

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unpredictable-AExtI-arm.txt

Added the missing bit definition for the 4th bit of the STR (post reg) instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions.

2012-05-11 09:28:27 +00:00

unpredictable-AI1cmp-arm.txt

Add suport for unpredicatble cases of the cmp, tst, teq and cmnz ARM instructions in the disassembler.

2012-04-18 12:48:43 +00:00

unpredictable-LDR-arm.txt

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unpredictable-LDRD-arm.txt

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unpredictable-LSL-regform.txt

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unpredictable-MRRC2-arm.txt

Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the disassembler. Since the upredicability conditions are complex, C++ code was added to handle them.

2012-04-18 13:12:50 +00:00

unpredictable-MRS-arm.txt

Fix the bahavior of the disassembler when decoding unpredictable mrs instructions on ARM. Now the diasassembler emmits warnings instead of errors.

2012-04-18 14:09:07 +00:00

unpredictable-MUL-arm.txt

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unpredictable-RSC-arm.txt

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unpredictable-SEL-arm.txt

Added the missing bit definition for the 4th bit of the STR (post reg) instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions.

2012-05-11 09:28:27 +00:00

unpredictable-SHADD16-arm.txt

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unpredictable-SSAT-arm.txt

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unpredictable-STRBrs-arm.txt

The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this.

2012-03-20 15:54:56 +00:00

unpredictable-swp-arm.txt

Added support for disassembling unpredictable swp/swpb ARM instructions.

2012-04-18 14:18:57 +00:00

unpredictable-UQADD8-arm.txt

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unpredictables-thumb.txt

Teach the MC and disassembler about SoftFail, and hook it up to UNPREDICTABLE on ARM. Wire this to tBLX in order to provide test coverage.

2012-02-09 10:56:31 +00:00

vfp4.txt

Fix a number of problems with ARM fused multiply add/subtract instructions.

2012-04-11 00:13:00 +00:00