Chris Lattner d1980a5acd Move 3 "(add (select cc, 0, c), x) -> (select cc, x, (add, x, c))" ...

related transformations out of target-specific dag combine into the
ARM backend.  These were added by Evan in r37685 with no testcases
and only seems to help ARM (e.g. test/CodeGen/ARM/select_xform.ll).

Add some simple X86-specific (for now) DAG combines that turn things
like cond ? 8 : 0  -> (zext(cond) << 3).  This happens frequently
with the recently added cp constant select optimization, but is a
very general xform.  For example, we now compile the second example
in const-select.ll to:

_test:
        movsd   LCPI2_0, %xmm0
        ucomisd 8(%esp), %xmm0
        seta    %al
        movzbl  %al, %eax
        movl    4(%esp), %ecx
        movsbl  (%ecx,%eax,4), %eax
        ret

instead of:

_test:
        movl    4(%esp), %eax
        leal    4(%eax), %ecx
        movsd   LCPI2_0, %xmm0
        ucomisd 8(%esp), %xmm0
        cmovbe  %eax, %ecx
        movsbl  (%ecx), %eax
        ret

This passes multisource and dejagnu.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66779 91177308-0d34-0410-b5e6-96231b3b80d8

2009-03-12 06:52:53 +00:00

..

CallingConvLower.cpp

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CMakeLists.txt

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DAGCombiner.cpp

Move 3 "(add (select cc, 0, c), x) -> (select cc, x, (add, x, c))"

2009-03-12 06:52:53 +00:00

FastISel.cpp

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LegalizeDAG.cpp

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LegalizeFloatTypes.cpp

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LegalizeIntegerTypes.cpp

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LegalizeTypes.cpp

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LegalizeTypes.h

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LegalizeTypesGeneric.cpp

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LegalizeVectorTypes.cpp

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Makefile

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ScheduleDAGFast.cpp

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ScheduleDAGList.cpp

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ScheduleDAGRRList.cpp

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ScheduleDAGSDNodes.cpp

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ScheduleDAGSDNodes.h

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ScheduleDAGSDNodesEmit.cpp

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SelectionDAG.cpp

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SelectionDAGBuild.cpp

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SelectionDAGBuild.h

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SelectionDAGISel.cpp

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SelectionDAGPrinter.cpp

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TargetLowering.cpp

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