Daniel Sanders 7eedd07d5e [mips] Add backend support for Mips32r[35] and Mips64r[35]. ... Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229695 91177308-0d34-0410-b5e6-96231b3b80d8		2015-02-18 16:24:50 +00:00
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AArch64
ARM
Hexagon
Mips	[mips] Add backend support for Mips32r[35] and Mips64r[35].	2015-02-18 16:24:50 +00:00
PowerPC	This patch adds the VSX logical instructions introduced in the Power ISA 2.07. It also removes the added complexity that favors VMX versions of the three instructions.	2015-02-18 16:21:46 +00:00
Sparc
SystemZ
X86	[X86] Add support for parsing and printing the mnemonic aliases for the XOP VPCOM instructions.	2015-02-13 07:42:25 +00:00
XCore