Chad Rosier 373fc00835 [AArch32] Add patterns for VCVT{A,N,P,M}. ...

Patterns for lowering libm calls to VCVT{A,N,P,M} are also included.
Phabricator Revision: http://reviews.llvm.org/D5033

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216388 91177308-0d34-0410-b5e6-96231b3b80d8

2014-08-25 16:56:33 +00:00

..

AArch64

[FastISel][AArch64] Add support for variable shift.

2014-08-21 23:06:07 +00:00

ARM

[AArch32] Add patterns for VCVT{A,N,P,M}.

2014-08-25 16:56:33 +00:00

CPP

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Generic

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Hexagon

DebugInfo: Assert that any CU for which debug_loc lists are emitted, has at least one range.

2014-08-06 00:21:25 +00:00

Inputs

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Mips

[mips] Don't use odd-numbered float registers for double arguments for fastcc

2014-08-22 09:23:22 +00:00

MSP430

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NVPTX

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PowerPC

[PowerPC] Add support for dcbtst and icbt (prefetch)

2014-08-23 23:21:04 +00:00

R600

R600/SI: Use READ2/WRITE2 instructions for 64-bit mem ops with 32-bit alignment

2014-08-22 18:49:35 +00:00

SPARC

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SystemZ

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Thumb

ARM / x86_64 varargs: Don't save regparms in prologue without va_start

2014-08-22 21:59:26 +00:00

Thumb2

ARM / x86_64 varargs: Don't save regparms in prologue without va_start

2014-08-22 21:59:26 +00:00

X86

[x86] Start fixing a really subtle and terrible form of miscompile in

2014-08-23 10:25:15 +00:00

XCore

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