mirror of
https://github.com/c64scene-ar/llvm-6502.git
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a7542d5f87
There are some that I didn't remove this round because they looked like obvious stubs. There are dead variables in gtest too, they should be fixed upstream. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158090 91177308-0d34-0410-b5e6-96231b3b80d8
327 lines
10 KiB
C++
327 lines
10 KiB
C++
//===-- MSP430InstrInfo.cpp - MSP430 Instruction Information --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the MSP430 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "MSP430InstrInfo.h"
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#include "MSP430.h"
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#include "MSP430MachineFunctionInfo.h"
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#include "MSP430TargetMachine.h"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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#define GET_INSTRINFO_CTOR
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#include "MSP430GenInstrInfo.inc"
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using namespace llvm;
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MSP430InstrInfo::MSP430InstrInfo(MSP430TargetMachine &tm)
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: MSP430GenInstrInfo(MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP),
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RI(tm, *this) {}
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void MSP430InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, bool isKill, int FrameIdx,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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DebugLoc DL;
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if (MI != MBB.end()) DL = MI->getDebugLoc();
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MachineFunction &MF = *MBB.getParent();
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MachineFrameInfo &MFI = *MF.getFrameInfo();
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MachineMemOperand *MMO =
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MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
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MachineMemOperand::MOStore,
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MFI.getObjectSize(FrameIdx),
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MFI.getObjectAlignment(FrameIdx));
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if (RC == &MSP430::GR16RegClass)
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BuildMI(MBB, MI, DL, get(MSP430::MOV16mr))
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.addFrameIndex(FrameIdx).addImm(0)
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.addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
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else if (RC == &MSP430::GR8RegClass)
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BuildMI(MBB, MI, DL, get(MSP430::MOV8mr))
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.addFrameIndex(FrameIdx).addImm(0)
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.addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
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else
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llvm_unreachable("Cannot store this register to stack slot!");
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}
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void MSP430InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIdx,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const{
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DebugLoc DL;
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if (MI != MBB.end()) DL = MI->getDebugLoc();
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MachineFunction &MF = *MBB.getParent();
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MachineFrameInfo &MFI = *MF.getFrameInfo();
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MachineMemOperand *MMO =
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MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
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MachineMemOperand::MOLoad,
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MFI.getObjectSize(FrameIdx),
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MFI.getObjectAlignment(FrameIdx));
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if (RC == &MSP430::GR16RegClass)
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BuildMI(MBB, MI, DL, get(MSP430::MOV16rm))
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.addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO);
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else if (RC == &MSP430::GR8RegClass)
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BuildMI(MBB, MI, DL, get(MSP430::MOV8rm))
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.addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO);
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else
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llvm_unreachable("Cannot store this register to stack slot!");
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}
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void MSP430InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const {
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unsigned Opc;
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if (MSP430::GR16RegClass.contains(DestReg, SrcReg))
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Opc = MSP430::MOV16rr;
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else if (MSP430::GR8RegClass.contains(DestReg, SrcReg))
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Opc = MSP430::MOV8rr;
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else
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llvm_unreachable("Impossible reg-to-reg copy");
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BuildMI(MBB, I, DL, get(Opc), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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}
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unsigned MSP430InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
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MachineBasicBlock::iterator I = MBB.end();
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unsigned Count = 0;
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while (I != MBB.begin()) {
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--I;
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if (I->isDebugValue())
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continue;
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if (I->getOpcode() != MSP430::JMP &&
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I->getOpcode() != MSP430::JCC &&
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I->getOpcode() != MSP430::Br &&
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I->getOpcode() != MSP430::Bm)
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break;
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// Remove the branch.
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I->eraseFromParent();
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I = MBB.end();
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++Count;
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}
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return Count;
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}
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bool MSP430InstrInfo::
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ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
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assert(Cond.size() == 1 && "Invalid Xbranch condition!");
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MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm());
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switch (CC) {
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default: llvm_unreachable("Invalid branch condition!");
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case MSP430CC::COND_E:
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CC = MSP430CC::COND_NE;
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break;
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case MSP430CC::COND_NE:
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CC = MSP430CC::COND_E;
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break;
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case MSP430CC::COND_L:
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CC = MSP430CC::COND_GE;
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break;
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case MSP430CC::COND_GE:
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CC = MSP430CC::COND_L;
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break;
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case MSP430CC::COND_HS:
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CC = MSP430CC::COND_LO;
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break;
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case MSP430CC::COND_LO:
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CC = MSP430CC::COND_HS;
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break;
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}
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Cond[0].setImm(CC);
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return false;
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}
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bool MSP430InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
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if (!MI->isTerminator()) return false;
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// Conditional branch is a special case.
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if (MI->isBranch() && !MI->isBarrier())
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return true;
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if (!MI->isPredicable())
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return true;
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return !isPredicated(MI);
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}
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bool MSP430InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const {
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// Start from the bottom of the block and work up, examining the
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// terminator instructions.
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MachineBasicBlock::iterator I = MBB.end();
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while (I != MBB.begin()) {
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--I;
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if (I->isDebugValue())
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continue;
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// Working from the bottom, when we see a non-terminator
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// instruction, we're done.
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if (!isUnpredicatedTerminator(I))
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break;
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// A terminator that isn't a branch can't easily be handled
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// by this analysis.
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if (!I->isBranch())
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return true;
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// Cannot handle indirect branches.
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if (I->getOpcode() == MSP430::Br ||
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I->getOpcode() == MSP430::Bm)
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return true;
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// Handle unconditional branches.
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if (I->getOpcode() == MSP430::JMP) {
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if (!AllowModify) {
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TBB = I->getOperand(0).getMBB();
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continue;
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}
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// If the block has any instructions after a JMP, delete them.
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while (llvm::next(I) != MBB.end())
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llvm::next(I)->eraseFromParent();
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Cond.clear();
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FBB = 0;
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// Delete the JMP if it's equivalent to a fall-through.
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if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
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TBB = 0;
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I->eraseFromParent();
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I = MBB.end();
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continue;
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}
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// TBB is used to indicate the unconditinal destination.
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TBB = I->getOperand(0).getMBB();
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continue;
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}
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// Handle conditional branches.
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assert(I->getOpcode() == MSP430::JCC && "Invalid conditional branch");
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MSP430CC::CondCodes BranchCode =
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static_cast<MSP430CC::CondCodes>(I->getOperand(1).getImm());
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if (BranchCode == MSP430CC::COND_INVALID)
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return true; // Can't handle weird stuff.
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// Working from the bottom, handle the first conditional branch.
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if (Cond.empty()) {
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FBB = TBB;
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TBB = I->getOperand(0).getMBB();
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Cond.push_back(MachineOperand::CreateImm(BranchCode));
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continue;
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}
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// Handle subsequent conditional branches. Only handle the case where all
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// conditional branches branch to the same destination.
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assert(Cond.size() == 1);
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assert(TBB);
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// Only handle the case where all conditional branches branch to
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// the same destination.
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if (TBB != I->getOperand(0).getMBB())
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return true;
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MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm();
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// If the conditions are the same, we can leave them alone.
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if (OldBranchCode == BranchCode)
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continue;
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return true;
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}
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return false;
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}
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unsigned
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MSP430InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL) const {
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// Shouldn't be a fall through.
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assert(TBB && "InsertBranch must not be told to insert a fallthrough");
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assert((Cond.size() == 1 || Cond.size() == 0) &&
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"MSP430 branch conditions have one component!");
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if (Cond.empty()) {
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// Unconditional branch?
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assert(!FBB && "Unconditional branch with multiple successors!");
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BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(TBB);
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return 1;
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}
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// Conditional branch.
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unsigned Count = 0;
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BuildMI(&MBB, DL, get(MSP430::JCC)).addMBB(TBB).addImm(Cond[0].getImm());
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++Count;
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if (FBB) {
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// Two-way Conditional branch. Insert the second branch.
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BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(FBB);
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++Count;
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}
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return Count;
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}
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/// GetInstSize - Return the number of bytes of code the specified
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/// instruction may be. This returns the maximum number of bytes.
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///
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unsigned MSP430InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
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const MCInstrDesc &Desc = MI->getDesc();
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switch (Desc.TSFlags & MSP430II::SizeMask) {
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default:
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switch (Desc.getOpcode()) {
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default: llvm_unreachable("Unknown instruction size!");
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case TargetOpcode::PROLOG_LABEL:
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case TargetOpcode::EH_LABEL:
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case TargetOpcode::IMPLICIT_DEF:
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case TargetOpcode::KILL:
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case TargetOpcode::DBG_VALUE:
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return 0;
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case TargetOpcode::INLINEASM: {
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const MachineFunction *MF = MI->getParent()->getParent();
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const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
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return TII.getInlineAsmLength(MI->getOperand(0).getSymbolName(),
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*MF->getTarget().getMCAsmInfo());
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}
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}
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case MSP430II::SizeSpecial:
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switch (MI->getOpcode()) {
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default: llvm_unreachable("Unknown instruction size!");
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case MSP430::SAR8r1c:
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case MSP430::SAR16r1c:
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return 4;
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}
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case MSP430II::Size2Bytes:
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return 2;
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case MSP430II::Size4Bytes:
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return 4;
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case MSP430II::Size6Bytes:
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return 6;
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}
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}
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