Bill Wendling 5991487c10 Make RegList an ASM operand so that TableGen will generate code for it. This is
an initial implementation and may change once reglists are fully fleshed out.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118390 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 00:39:58 +00:00
..
2010-11-06 11:45:59 +00:00