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276365dd4b
be the first encoded as the first feature. It then uses the CPU name to look up features / scheduling itineray even though clients know full well the CPU name being used to query these properties. The fix is to just have the clients explictly pass the CPU name! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134127 91177308-0d34-0410-b5e6-96231b3b80d8
71 lines
2.6 KiB
C++
71 lines
2.6 KiB
C++
//===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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#include "Sparc.h"
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#include "SparcMCAsmInfo.h"
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#include "SparcTargetMachine.h"
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#include "llvm/PassManager.h"
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#include "llvm/Target/TargetRegistry.h"
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using namespace llvm;
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extern "C" void LLVMInitializeSparcTarget() {
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// Register the target.
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RegisterTargetMachine<SparcV8TargetMachine> X(TheSparcTarget);
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RegisterTargetMachine<SparcV9TargetMachine> Y(TheSparcV9Target);
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RegisterAsmInfo<SparcELFMCAsmInfo> A(TheSparcTarget);
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RegisterAsmInfo<SparcELFMCAsmInfo> B(TheSparcV9Target);
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}
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/// SparcTargetMachine ctor - Create an ILP32 architecture model
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///
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SparcTargetMachine::SparcTargetMachine(const Target &T, const std::string &TT,
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const std::string &CPU,
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const std::string &FS, bool is64bit)
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: LLVMTargetMachine(T, TT),
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Subtarget(TT, CPU, FS, is64bit),
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DataLayout(Subtarget.getDataLayout()),
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TLInfo(*this), TSInfo(*this), InstrInfo(Subtarget),
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FrameLowering(Subtarget) {
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}
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bool SparcTargetMachine::addInstSelector(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel) {
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PM.add(createSparcISelDag(*this));
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return false;
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}
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/// addPreEmitPass - This pass may be implemented by targets that want to run
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/// passes immediately before machine code is emitted. This should return
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/// true if -print-machineinstrs should print out the code after the passes.
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bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel){
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PM.add(createSparcFPMoverPass(*this));
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PM.add(createSparcDelaySlotFillerPass(*this));
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return true;
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}
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SparcV8TargetMachine::SparcV8TargetMachine(const Target &T,
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const std::string &TT,
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const std::string &CPU,
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const std::string &FS)
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: SparcTargetMachine(T, TT, CPU, FS, false) {
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}
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SparcV9TargetMachine::SparcV9TargetMachine(const Target &T,
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const std::string &TT,
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const std::string &CPU,
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const std::string &FS)
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: SparcTargetMachine(T, TT, CPU, FS, true) {
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}
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