Colin LeMahieu 504c77f9c8 [Hexagon] Adding tstbit/bitclr/bitset instructions. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224374 91177308-0d34-0410-b5e6-96231b3b80d8		2014-12-16 21:28:58 +00:00
..
AArch64
ARM	ARM: diagnose deprecated syntax	2014-12-16 05:53:25 +00:00
AsmParser
COFF	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00
Disassembler	[Hexagon] Adding tstbit/bitclr/bitset instructions.	2014-12-16 21:28:58 +00:00
ELF	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00
Hexagon	[Hexagon] Updating predicate register transfers and adding tstbit to allow select selection. Updating ll tests with predicate transfers that previously had nop encodings.	2014-12-09 18:16:49 +00:00
MachO	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00
Markup
Mips	[mips][microMIPS] Implement SWP and LWP instructions	2014-12-16 14:59:10 +00:00
PowerPC	[PowerPC] Add asm support for cache-inhibited ld/st instructions	2014-11-30 10:15:56 +00:00
R600
Sparc
SystemZ
X86	[MC] Reset the MCInst in the matcher function before adding opcode/operands.	2014-12-16 18:05:28 +00:00