llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-06 23:32:27 +00:00

History

Chad Rosier b29b950bf2 Add support for emitting both signed- and zero-extend loads. Fix

SimplifyAddress to handle either a 12-bit unsigned offset or the ARM +/-imm8
offsets (addressing mode 3).  This enables a load followed by an integer 
extend to be folded into a single load.

For example:
ldrb r1, [r0]       ldrb r1, [r0]
uxtb r2, r1     =>
mov  r3, r2         mov  r3, r1


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144488 91177308-0d34-0410-b5e6-96231b3b80d8

2011-11-13 02:23:59 +00:00

Analysis

Don't forget to check FlagNW when determining whether an AddRecExpr will wrap

2011-11-09 07:11:37 +00:00