llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-23 05:29:23 +00:00

History

Hal Finkel 5cad12d12a Fix PPC64 64-bit GPR inline asm constraint matching

Internally, the PowerPC backend names the 32-bit GPRs R[0-9]+, and names the
64-bit parent GPRs X[0-9]+. When matching inline assembly constraints with
explicit register names, on PPC64 when an i64 MVT has been requested, we need
to follow gcc's convention of using r[0-9]+ to refer to the 64-bit (parent)
registers.

At some point, we'll probably want to arrange things so that the generic code
in TargetLowering uses the AsmName fields declared in *RegisterInfo.td in order
to match these inline asm register constraints. If we do that, this change can
be reverted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187693 91177308-0d34-0410-b5e6-96231b3b80d8

2013-08-03 12:25:10 +00:00

Analysis

Minor address space code simplification.

2013-08-03 01:03:12 +00:00

AsmParser

Target/X86: Add explicit Win64 and System V/x86-64 calling conventions.

2013-07-12 06:02:35 +00:00

Bitcode

Make .bc en/decoding of AttrKind stable

2013-07-26 04:16:55 +00:00

CodeGen

Bugfix for making the DWARF debug strings and labels to code emitted as secrel32 instead of long opcodes (only for coff). This makes them debuggable with GDB (with fix for 64bits msvc)