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llvm-6502/lib/Target
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Vikram S. Adve b7f06f46a1 Fixed instruction information for RDCCR and WRCCR. 
Fixed selection to create a TmpInstruction for each integer CC register
(since it is an implicit side-effect, unlike FP CC registers which are
explicit operands).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1120 91177308-0d34-0410-b5e6-96231b3b80d8
2001-11-04 19:34:49 +00:00
..
SparcV9
Fixed instruction information for RDCCR and WRCCR.
2001-11-04 19:34:49 +00:00
Makefile
Make a new llvm/Target #include directory.
2001-09-14 05:34:53 +00:00
TargetData.cpp
Commit more code over to new cast style
2001-10-02 03:41:24 +00:00
TargetMachine.cpp
Renamed files to match the main classes they provide.
2001-09-18 12:58:33 +00:00
TargetSchedInfo.cpp
Renamed files to match the main classes they provide.
2001-09-18 12:58:33 +00:00