mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-11-04 05:17:07 +00:00
67a6103a34
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83528 91177308-0d34-0410-b5e6-96231b3b80d8
126 lines
4.4 KiB
LLVM
126 lines
4.4 KiB
LLVM
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
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define <4 x i16> @vpadals8(<4 x i16>* %A, <8 x i8>* %B) nounwind {
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;CHECK: vpadals8:
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;CHECK: vpadal.s8
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = call <4 x i16> @llvm.arm.neon.vpadals.v4i16.v8i8(<4 x i16> %tmp1, <8 x i8> %tmp2)
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ret <4 x i16> %tmp3
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}
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define <2 x i32> @vpadals16(<2 x i32>* %A, <4 x i16>* %B) nounwind {
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;CHECK: vpadals16:
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;CHECK: vpadal.s16
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%tmp1 = load <2 x i32>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = call <2 x i32> @llvm.arm.neon.vpadals.v2i32.v4i16(<2 x i32> %tmp1, <4 x i16> %tmp2)
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ret <2 x i32> %tmp3
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}
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define <1 x i64> @vpadals32(<1 x i64>* %A, <2 x i32>* %B) nounwind {
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;CHECK: vpadals32:
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;CHECK: vpadal.s32
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%tmp1 = load <1 x i64>* %A
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%tmp2 = load <2 x i32>* %B
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%tmp3 = call <1 x i64> @llvm.arm.neon.vpadals.v1i64.v2i32(<1 x i64> %tmp1, <2 x i32> %tmp2)
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ret <1 x i64> %tmp3
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}
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define <4 x i16> @vpadalu8(<4 x i16>* %A, <8 x i8>* %B) nounwind {
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;CHECK: vpadalu8:
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;CHECK: vpadal.u8
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = call <4 x i16> @llvm.arm.neon.vpadalu.v4i16.v8i8(<4 x i16> %tmp1, <8 x i8> %tmp2)
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ret <4 x i16> %tmp3
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}
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define <2 x i32> @vpadalu16(<2 x i32>* %A, <4 x i16>* %B) nounwind {
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;CHECK: vpadalu16:
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;CHECK: vpadal.u16
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%tmp1 = load <2 x i32>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = call <2 x i32> @llvm.arm.neon.vpadalu.v2i32.v4i16(<2 x i32> %tmp1, <4 x i16> %tmp2)
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ret <2 x i32> %tmp3
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}
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define <1 x i64> @vpadalu32(<1 x i64>* %A, <2 x i32>* %B) nounwind {
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;CHECK: vpadalu32:
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;CHECK: vpadal.u32
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%tmp1 = load <1 x i64>* %A
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%tmp2 = load <2 x i32>* %B
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%tmp3 = call <1 x i64> @llvm.arm.neon.vpadalu.v1i64.v2i32(<1 x i64> %tmp1, <2 x i32> %tmp2)
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ret <1 x i64> %tmp3
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}
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define <8 x i16> @vpadalQs8(<8 x i16>* %A, <16 x i8>* %B) nounwind {
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;CHECK: vpadalQs8:
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;CHECK: vpadal.s8
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <16 x i8>* %B
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%tmp3 = call <8 x i16> @llvm.arm.neon.vpadals.v8i16.v16i8(<8 x i16> %tmp1, <16 x i8> %tmp2)
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ret <8 x i16> %tmp3
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}
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define <4 x i32> @vpadalQs16(<4 x i32>* %A, <8 x i16>* %B) nounwind {
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;CHECK: vpadalQs16:
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;CHECK: vpadal.s16
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <8 x i16>* %B
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%tmp3 = call <4 x i32> @llvm.arm.neon.vpadals.v4i32.v8i16(<4 x i32> %tmp1, <8 x i16> %tmp2)
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ret <4 x i32> %tmp3
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}
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define <2 x i64> @vpadalQs32(<2 x i64>* %A, <4 x i32>* %B) nounwind {
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;CHECK: vpadalQs32:
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;CHECK: vpadal.s32
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%tmp1 = load <2 x i64>* %A
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%tmp2 = load <4 x i32>* %B
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%tmp3 = call <2 x i64> @llvm.arm.neon.vpadals.v2i64.v4i32(<2 x i64> %tmp1, <4 x i32> %tmp2)
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ret <2 x i64> %tmp3
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}
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define <8 x i16> @vpadalQu8(<8 x i16>* %A, <16 x i8>* %B) nounwind {
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;CHECK: vpadalQu8:
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;CHECK: vpadal.u8
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <16 x i8>* %B
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%tmp3 = call <8 x i16> @llvm.arm.neon.vpadalu.v8i16.v16i8(<8 x i16> %tmp1, <16 x i8> %tmp2)
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ret <8 x i16> %tmp3
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}
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define <4 x i32> @vpadalQu16(<4 x i32>* %A, <8 x i16>* %B) nounwind {
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;CHECK: vpadalQu16:
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;CHECK: vpadal.u16
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <8 x i16>* %B
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%tmp3 = call <4 x i32> @llvm.arm.neon.vpadalu.v4i32.v8i16(<4 x i32> %tmp1, <8 x i16> %tmp2)
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ret <4 x i32> %tmp3
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}
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define <2 x i64> @vpadalQu32(<2 x i64>* %A, <4 x i32>* %B) nounwind {
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;CHECK: vpadalQu32:
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;CHECK: vpadal.u32
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%tmp1 = load <2 x i64>* %A
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%tmp2 = load <4 x i32>* %B
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%tmp3 = call <2 x i64> @llvm.arm.neon.vpadalu.v2i64.v4i32(<2 x i64> %tmp1, <4 x i32> %tmp2)
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ret <2 x i64> %tmp3
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}
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declare <4 x i16> @llvm.arm.neon.vpadals.v4i16.v8i8(<4 x i16>, <8 x i8>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vpadals.v2i32.v4i16(<2 x i32>, <4 x i16>) nounwind readnone
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declare <1 x i64> @llvm.arm.neon.vpadals.v1i64.v2i32(<1 x i64>, <2 x i32>) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vpadalu.v4i16.v8i8(<4 x i16>, <8 x i8>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vpadalu.v2i32.v4i16(<2 x i32>, <4 x i16>) nounwind readnone
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declare <1 x i64> @llvm.arm.neon.vpadalu.v1i64.v2i32(<1 x i64>, <2 x i32>) nounwind readnone
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declare <8 x i16> @llvm.arm.neon.vpadals.v8i16.v16i8(<8 x i16>, <16 x i8>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vpadals.v4i32.v8i16(<4 x i32>, <8 x i16>) nounwind readnone
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declare <2 x i64> @llvm.arm.neon.vpadals.v2i64.v4i32(<2 x i64>, <4 x i32>) nounwind readnone
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declare <8 x i16> @llvm.arm.neon.vpadalu.v8i16.v16i8(<8 x i16>, <16 x i8>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vpadalu.v4i32.v8i16(<4 x i32>, <8 x i16>) nounwind readnone
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declare <2 x i64> @llvm.arm.neon.vpadalu.v2i64.v4i32(<2 x i64>, <4 x i32>) nounwind readnone
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