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bd48d31b37
Summary:
Highlights:
- Registers are resolved much later (by the render method).
Prior to that point, GPR32's/GPR64's are GPR's regardless of register
size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register
size or FR mode. Numeric registers can be anything.
- All registers are parsed the same way everywhere (even when handling
symbol aliasing)
- One consequence is that all registers can be specified numerically
almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing
but that can be easily resolved.
- Removes the need for the hasConsumedDollar hack
- Parenthesis and Bracket suffixes are handled generically
- Micromips instructions are parsed directly instead of going through the
standard encodings first.
- rdhwr accepts all 32 registers, and the following instructions that previously
xfailed now work:
ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d,
c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1
- Diagnostics involving registers point at the correct character (the $)
- There's only one kind of immediate in MipsOperand. LSA immediates are handled
by the predicate and renderer.
Lowlights:
- Hardcoded '$zero' in the div patterns is handled with a hack.
MipsOperand::isReg() will return true for a k_RegisterIndex token
with Index == 0 and getReg() will return ZERO for this case. Note that it
doesn't return ZERO_64 on isGP64() targets.
- I haven't cleaned up all of the now-unused functions.
Some more of the generic parser could be removed too (integers and relocs
for example).
- insve.df needed a custom decoder to handle the implicit fourth operand that
was needed to make it parse correctly. The difficulty was that the matcher
expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this.
Reviewers: matheusalmeida, vmedic
Reviewed By: matheusalmeida
Differential Revision: http://llvm-reviews.chandlerc.com/D3222
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205292 91177308-0d34-0410-b5e6-96231b3b80d8
57 lines
1.3 KiB
ArmAsm
57 lines
1.3 KiB
ArmAsm
# Instructions that should be valid but currently fail for known reasons (e.g.
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# they aren't implemented yet).
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# This test is set up to XPASS if any instruction generates an encoding.
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#
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# FIXME: Test MIPS-IV instead of MIPS64
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# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64 | not FileCheck %s
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# CHECK-NOT: encoding
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# XFAIL: *
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.set noat
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c.eq.d $fcc1,$f15,$f15
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c.eq.s $fcc5,$f24,$f17
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c.f.d $fcc4,$f11,$f21
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c.f.s $fcc4,$f30,$f7
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c.le.d $fcc4,$f18,$f1
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c.le.s $fcc6,$f24,$f4
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c.lt.d $fcc3,$f9,$f3
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c.lt.s $fcc2,$f17,$f14
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c.nge.d $fcc5,$f21,$f16
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c.nge.s $fcc3,$f11,$f8
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c.ngl.s $fcc2,$f31,$f23
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c.ngle.s $fcc2,$f18,$f23
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c.ngt.d $fcc4,$f24,$f7
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c.ngt.s $fcc5,$f8,$f13
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c.ole.d $fcc2,$f16,$f31
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c.ole.s $fcc3,$f7,$f20
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c.olt.d $fcc4,$f19,$f28
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c.olt.s $fcc6,$f20,$f7
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c.seq.d $fcc4,$f31,$f7
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c.seq.s $fcc7,$f1,$f25
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c.ueq.d $fcc4,$f13,$f25
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c.ueq.s $fcc6,$f3,$f30
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c.ule.d $fcc7,$f25,$f18
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c.ule.s $fcc7,$f21,$f30
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c.ult.d $fcc6,$f6,$f17
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c.ult.s $fcc7,$f24,$f10
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c.un.d $fcc6,$f23,$f24
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c.un.s $fcc1,$f30,$f4
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ehb
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madd.d $f18,$f19,$f26,$f20
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madd.s $f1,$f31,$f19,$f25
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msub.d $f10,$f1,$f31,$f18
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msub.s $f12,$f19,$f10,$f16
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nmadd.d $f18,$f9,$f14,$f19
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nmadd.s $f0,$f5,$f25,$f12
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nmsub.d $f30,$f8,$f16,$f30
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nmsub.s $f1,$f24,$f19,$f4
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recip.d $f19,$f6
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recip.s $f3,$f30
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rsqrt.d $f3,$f28
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rsqrt.s $f4,$f8
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ssnop
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tlbp
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tlbr
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tlbwi
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tlbwr
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