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https://github.com/c64scene-ar/llvm-6502.git
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d714fcf5c8
Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first several times this was committed (e.g. r229831, r233055), it caused several buildbot failures. Apparently the reason for most failures was both clang and gcc's inability to deal with large numbers (> 10K) of bitset constructor calls in tablegen-generated initializers of instruction info tables. This should now be fixed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238192 91177308-0d34-0410-b5e6-96231b3b80d8
287 lines
8.9 KiB
C++
287 lines
8.9 KiB
C++
//===-- X86ATTInstPrinter.cpp - AT&T assembly instruction printing --------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file includes code for rendering MCInst instances as AT&T-style
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// assembly.
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//
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//===----------------------------------------------------------------------===//
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#include "X86ATTInstPrinter.h"
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#include "MCTargetDesc/X86BaseInfo.h"
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#include "MCTargetDesc/X86MCTargetDesc.h"
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#include "X86InstComments.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/Format.h"
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#include "llvm/Support/FormattedStream.h"
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#include <map>
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using namespace llvm;
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#define DEBUG_TYPE "asm-printer"
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// Include the auto-generated portion of the assembly writer.
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#define PRINT_ALIAS_INSTR
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#include "X86GenAsmWriter.inc"
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void X86ATTInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
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OS << markup("<reg:") << '%' << getRegisterName(RegNo) << markup(">");
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}
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void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
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StringRef Annot, const MCSubtargetInfo &STI) {
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const MCInstrDesc &Desc = MII.get(MI->getOpcode());
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uint64_t TSFlags = Desc.TSFlags;
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// If verbose assembly is enabled, we can print some informative comments.
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if (CommentStream)
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HasCustomInstComment =
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EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
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if (TSFlags & X86II::LOCK)
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OS << "\tlock\n";
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// Output CALLpcrel32 as "callq" in 64-bit mode.
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// In Intel annotation it's always emitted as "call".
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//
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// TODO: Probably this hack should be redesigned via InstAlias in
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// InstrInfo.td as soon as Requires clause is supported properly
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// for InstAlias.
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if (MI->getOpcode() == X86::CALLpcrel32 &&
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(STI.getFeatureBits()[X86::Mode64Bit])) {
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OS << "\tcallq\t";
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printPCRelImm(MI, 0, OS);
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}
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// Try to print any aliases first.
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else if (!printAliasInstr(MI, OS))
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printInstruction(MI, OS);
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// Next always print the annotation.
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printAnnotation(OS, Annot);
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}
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void X86ATTInstPrinter::printSSEAVXCC(const MCInst *MI, unsigned Op,
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raw_ostream &O) {
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int64_t Imm = MI->getOperand(Op).getImm();
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switch (Imm) {
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default: llvm_unreachable("Invalid ssecc/avxcc argument!");
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case 0: O << "eq"; break;
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case 1: O << "lt"; break;
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case 2: O << "le"; break;
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case 3: O << "unord"; break;
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case 4: O << "neq"; break;
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case 5: O << "nlt"; break;
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case 6: O << "nle"; break;
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case 7: O << "ord"; break;
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case 8: O << "eq_uq"; break;
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case 9: O << "nge"; break;
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case 0xa: O << "ngt"; break;
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case 0xb: O << "false"; break;
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case 0xc: O << "neq_oq"; break;
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case 0xd: O << "ge"; break;
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case 0xe: O << "gt"; break;
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case 0xf: O << "true"; break;
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case 0x10: O << "eq_os"; break;
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case 0x11: O << "lt_oq"; break;
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case 0x12: O << "le_oq"; break;
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case 0x13: O << "unord_s"; break;
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case 0x14: O << "neq_us"; break;
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case 0x15: O << "nlt_uq"; break;
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case 0x16: O << "nle_uq"; break;
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case 0x17: O << "ord_s"; break;
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case 0x18: O << "eq_us"; break;
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case 0x19: O << "nge_uq"; break;
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case 0x1a: O << "ngt_uq"; break;
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case 0x1b: O << "false_os"; break;
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case 0x1c: O << "neq_os"; break;
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case 0x1d: O << "ge_oq"; break;
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case 0x1e: O << "gt_oq"; break;
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case 0x1f: O << "true_us"; break;
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}
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}
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void X86ATTInstPrinter::printXOPCC(const MCInst *MI, unsigned Op,
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raw_ostream &O) {
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int64_t Imm = MI->getOperand(Op).getImm();
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switch (Imm) {
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default: llvm_unreachable("Invalid xopcc argument!");
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case 0: O << "lt"; break;
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case 1: O << "le"; break;
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case 2: O << "gt"; break;
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case 3: O << "ge"; break;
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case 4: O << "eq"; break;
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case 5: O << "neq"; break;
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case 6: O << "false"; break;
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case 7: O << "true"; break;
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}
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}
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void X86ATTInstPrinter::printRoundingControl(const MCInst *MI, unsigned Op,
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raw_ostream &O) {
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int64_t Imm = MI->getOperand(Op).getImm() & 0x3;
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switch (Imm) {
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case 0: O << "{rn-sae}"; break;
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case 1: O << "{rd-sae}"; break;
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case 2: O << "{ru-sae}"; break;
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case 3: O << "{rz-sae}"; break;
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}
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}
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/// printPCRelImm - This is used to print an immediate value that ends up
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/// being encoded as a pc-relative value (e.g. for jumps and calls). These
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/// print slightly differently than normal immediates. For example, a $ is not
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/// emitted.
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void X86ATTInstPrinter::printPCRelImm(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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const MCOperand &Op = MI->getOperand(OpNo);
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if (Op.isImm())
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O << formatImm(Op.getImm());
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else {
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assert(Op.isExpr() && "unknown pcrel immediate operand");
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// If a symbolic branch target was added as a constant expression then print
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// that address in hex.
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const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
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int64_t Address;
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if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) {
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O << formatHex((uint64_t)Address);
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} else {
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// Otherwise, just print the expression.
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O << *Op.getExpr();
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}
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}
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}
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void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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const MCOperand &Op = MI->getOperand(OpNo);
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if (Op.isReg()) {
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printRegName(O, Op.getReg());
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} else if (Op.isImm()) {
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// Print X86 immediates as signed values.
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O << markup("<imm:") << '$' << formatImm((int64_t)Op.getImm())
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<< markup(">");
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// If there are no instruction-specific comments, add a comment clarifying
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// the hex value of the immediate operand when it isn't in the range
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// [-256,255].
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if (CommentStream && !HasCustomInstComment &&
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(Op.getImm() > 255 || Op.getImm() < -256))
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*CommentStream << format("imm = 0x%" PRIX64 "\n", (uint64_t)Op.getImm());
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} else {
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assert(Op.isExpr() && "unknown operand kind in printOperand");
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O << markup("<imm:") << '$' << *Op.getExpr() << markup(">");
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}
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}
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void X86ATTInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
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raw_ostream &O) {
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const MCOperand &BaseReg = MI->getOperand(Op + X86::AddrBaseReg);
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const MCOperand &IndexReg = MI->getOperand(Op + X86::AddrIndexReg);
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const MCOperand &DispSpec = MI->getOperand(Op + X86::AddrDisp);
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const MCOperand &SegReg = MI->getOperand(Op + X86::AddrSegmentReg);
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O << markup("<mem:");
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// If this has a segment register, print it.
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if (SegReg.getReg()) {
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printOperand(MI, Op + X86::AddrSegmentReg, O);
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O << ':';
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}
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if (DispSpec.isImm()) {
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int64_t DispVal = DispSpec.getImm();
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if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
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O << formatImm(DispVal);
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} else {
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assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
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O << *DispSpec.getExpr();
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}
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if (IndexReg.getReg() || BaseReg.getReg()) {
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O << '(';
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if (BaseReg.getReg())
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printOperand(MI, Op + X86::AddrBaseReg, O);
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if (IndexReg.getReg()) {
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O << ',';
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printOperand(MI, Op + X86::AddrIndexReg, O);
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unsigned ScaleVal = MI->getOperand(Op + X86::AddrScaleAmt).getImm();
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if (ScaleVal != 1) {
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O << ',' << markup("<imm:") << ScaleVal // never printed in hex.
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<< markup(">");
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}
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}
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O << ')';
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}
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O << markup(">");
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}
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void X86ATTInstPrinter::printSrcIdx(const MCInst *MI, unsigned Op,
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raw_ostream &O) {
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const MCOperand &SegReg = MI->getOperand(Op + 1);
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O << markup("<mem:");
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// If this has a segment register, print it.
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if (SegReg.getReg()) {
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printOperand(MI, Op + 1, O);
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O << ':';
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}
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O << "(";
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printOperand(MI, Op, O);
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O << ")";
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O << markup(">");
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}
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void X86ATTInstPrinter::printDstIdx(const MCInst *MI, unsigned Op,
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raw_ostream &O) {
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O << markup("<mem:");
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O << "%es:(";
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printOperand(MI, Op, O);
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O << ")";
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O << markup(">");
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}
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void X86ATTInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
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raw_ostream &O) {
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const MCOperand &DispSpec = MI->getOperand(Op);
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const MCOperand &SegReg = MI->getOperand(Op + 1);
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O << markup("<mem:");
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// If this has a segment register, print it.
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if (SegReg.getReg()) {
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printOperand(MI, Op + 1, O);
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O << ':';
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}
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if (DispSpec.isImm()) {
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O << formatImm(DispSpec.getImm());
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} else {
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assert(DispSpec.isExpr() && "non-immediate displacement?");
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O << *DispSpec.getExpr();
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}
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O << markup(">");
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}
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void X86ATTInstPrinter::printU8Imm(const MCInst *MI, unsigned Op,
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raw_ostream &O) {
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O << markup("<imm:") << '$' << formatImm(MI->getOperand(Op).getImm() & 0xff)
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<< markup(">");
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}
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