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https://github.com/c64scene-ar/llvm-6502.git
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a22657f457
In historical reason, tblgen is not strictly required to be free from memory leaks. For now, I mark them as XFAIL, they could be fixed, though. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194353 91177308-0d34-0410-b5e6-96231b3b80d8
104 lines
3.0 KiB
TableGen
104 lines
3.0 KiB
TableGen
// RUN: llvm-tblgen %s | FileCheck %s
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// XFAIL: vg_leak
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// CHECK: [(set VR128:$dst, (int_x86_sse2_add_pd VR128:$src1, VR128:$src2))]
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// CHECK-NOT: [(set VR128:$dst, (int_x86_sse2_add_pd VR128:$src1, VR128:$src2))]
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// CHECK: [(set VR128:$dst, (int_x86_sse2_add_ps VR128:$src1, VR128:$src2))]
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// CHECK-NOT: [(set VR128:$dst, (int_x86_sse2_add_ps VR128:$src1, VR128:$src2))]
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class ValueType<int size, int value> {
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int Size = size;
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int Value = value;
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}
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def v2i64 : ValueType<128, 22>; // 2 x i64 vector value
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def v2f64 : ValueType<128, 28>; // 2 x f64 vector value
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class Intrinsic<string name> {
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string Name = name;
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}
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class Inst<bits<8> opcode, dag oopnds, dag iopnds, string asmstr,
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list<dag> pattern> {
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bits<8> Opcode = opcode;
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dag OutOperands = oopnds;
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dag InOperands = iopnds;
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string AssemblyString = asmstr;
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list<dag> Pattern = pattern;
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}
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def ops;
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def outs;
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def ins;
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def set;
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// Define registers
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class Register<string n> {
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string Name = n;
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}
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class RegisterClass<list<ValueType> regTypes, list<Register> regList> {
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list<ValueType> RegTypes = regTypes;
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list<Register> MemberList = regList;
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}
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def XMM0: Register<"xmm0">;
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def XMM1: Register<"xmm1">;
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def XMM2: Register<"xmm2">;
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def XMM3: Register<"xmm3">;
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def XMM4: Register<"xmm4">;
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def XMM5: Register<"xmm5">;
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def XMM6: Register<"xmm6">;
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def XMM7: Register<"xmm7">;
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def XMM8: Register<"xmm8">;
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def XMM9: Register<"xmm9">;
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def XMM10: Register<"xmm10">;
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def XMM11: Register<"xmm11">;
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def XMM12: Register<"xmm12">;
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def XMM13: Register<"xmm13">;
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def XMM14: Register<"xmm14">;
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def XMM15: Register<"xmm15">;
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def VR128 : RegisterClass<[v2i64, v2f64],
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[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
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XMM8, XMM9, XMM10, XMM11,
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XMM12, XMM13, XMM14, XMM15]>;
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// Dummy for subst
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def REGCLASS : RegisterClass<[], []>;
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class decls {
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// Dummy for foreach
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dag pattern;
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int operand;
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}
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def Decls : decls;
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// Define intrinsics
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def int_x86_sse2_add_ps : Intrinsic<"addps">;
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def int_x86_sse2_add_pd : Intrinsic<"addpd">;
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def INTRINSIC : Intrinsic<"Dummy">;
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multiclass arith<bits<8> opcode, string asmstr, string intr, list<dag> patterns> {
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def PS : Inst<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
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!strconcat(asmstr, "\t$dst, $src1, $src2"),
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!foreach(Decls.pattern, patterns,
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!foreach(Decls.operand, Decls.pattern,
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!subst(INTRINSIC, !cast<Intrinsic>(!subst("SUFFIX", "_ps", intr)),
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!subst(REGCLASS, VR128, Decls.operand))))>;
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def PD : Inst<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
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!strconcat(asmstr, "\t$dst, $src1, $src2"),
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!foreach(Decls.pattern, patterns,
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!foreach(Decls.operand, Decls.pattern,
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!subst(INTRINSIC, !cast<Intrinsic>(!subst("SUFFIX", "_pd", intr)),
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!subst(REGCLASS, VR128, Decls.operand))))>;
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}
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defm ADD : arith<0x58, "add", "int_x86_sse2_addSUFFIX",
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[(set REGCLASS:$dst, (INTRINSIC REGCLASS:$src1, REGCLASS:$src2))]>;
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