llvm-6502

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History

Bill Schmidt 808d878a96 [PPC64] Fix PR20071 (fctiduz generated for targets lacking that instruction)

PR20071 identifies a problem in PowerPC's fast-isel implementation for
floating-point conversion to integer.  The fctiduz instruction was added in
Power ISA 2.06 (i.e., Power7 and later).  However, this instruction is being
generated regardless of which 64-bit PowerPC target is selected.

The intent is for fast-isel to punt to DAG selection when this instruction is
not available.  This patch implements that change.  For testing purposes, the
existing fast-isel-conversion.ll test adds a RUN line for -mcpu=970 and tests
for the expected code generation.  Additionally, the existing test
fast-isel-conversion-p5.ll was found to be incorrectly expecting the
unavailable instruction to be generated.  I've removed these test variants
since we have adequate coverage in fast-isel-conversion.ll.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211627 91177308-0d34-0410-b5e6-96231b3b80d8

2014-06-24 20:05:18 +00:00

Analysis

Support: Move class ScaledNumber

2014-06-24 00:38:09 +00:00

AsmParser

…

Bitcode

Make ObjectFile and BitcodeReader always own the MemoryBuffer.

2014-06-23 21:53:12 +00:00

CodeGen

CodeGen: Avoid multiple strlen calls

2014-06-24 16:01:53 +00:00