Nate Begeman d5ce204c5f Don't generate operations that aren't yet supported ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23858 91177308-0d34-0410-b5e6-96231b3b80d8

2005-10-21 01:52:45 +00:00

..

Alpha

Kill some now-dead code.

2005-10-21 01:52:20 +00:00

CBackend

fix CBackend/2005-09-27-VolatileFuncPtr.ll

2005-09-27 20:52:44 +00:00

IA64

Don't generate operations that aren't yet supported

2005-10-21 01:52:45 +00:00

PowerPC

Invert the TargetLowering flag that controls divide by consant expansion.

2005-10-21 00:02:42 +00:00

Skeleton

CR registers are not used by this "target"

2005-09-30 06:43:58 +00:00

Sparc

silence some warnings

2005-10-05 17:15:09 +00:00

SparcV8

silence some warnings

2005-10-05 17:15:09 +00:00

SparcV9

This fixes PR638:

2005-10-19 20:07:15 +00:00

X86

Invert the TargetLowering flag that controls divide by consant expansion.

2005-10-21 00:02:42 +00:00

Makefile

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MRegisterInfo.cpp

Rename MRegisterDesc -> TargetRegisterDesc for consistency

2005-09-30 17:49:27 +00:00

SubtargetFeature.cpp

Print:

2005-09-07 05:44:14 +00:00

Target.td

Added InstrSchedClass to each of the PowerPC Instructions.

2005-10-19 19:51:16 +00:00

TargetData.cpp

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TargetFrameInfo.cpp

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TargetInstrInfo.cpp

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TargetMachine.cpp

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TargetMachineRegistry.cpp

1. Use SubtargetFeatures in llc/lli.

2005-09-01 21:38:21 +00:00

TargetSchedInfo.cpp

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TargetSchedule.td

Push processor descriptions to the top of target and add command line info.

2005-10-19 13:34:52 +00:00

TargetSelectionDAG.td

Use a literal to define ineg instead of immzero

2005-10-20 23:30:37 +00:00

TargetSubtarget.cpp

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