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65fc36b64afd0335a93b82e12e93f4894ebb9683
llvm-6502/lib/CodeGen/SelectionDAG
History
Chris Lattner 61a4c072b9 allow SRL to simplify its operands, as it doesn't demand all bits as input.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36245 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-18 03:06:49 +00:00
..
CallingConvLower.cpp
add methods for analysis of call results and return nodes.
2007-02-28 07:09:40 +00:00
DAGCombiner.cpp
allow SRL to simplify its operands, as it doesn't demand all bits as input.
2007-04-18 03:06:49 +00:00
LegalizeDAG.cpp
1. Insert custom lowering hooks for ISD::ROTR and ISD::ROTL.
2007-04-02 21:36:32 +00:00
Makefile
For PR780:
2006-07-26 16:18:00 +00:00
ScheduleDAG.cpp
Fix some VC++ warnings.
2007-03-20 20:43:18 +00:00
ScheduleDAGList.cpp
switch the sched unit map over to use a DenseMap instead of std::map. This
2007-02-03 01:34:13 +00:00
ScheduleDAGRRList.cpp
Estimate a cost using the possible number of scratch registers required and use
2007-03-14 22:43:40 +00:00
ScheduleDAGSimple.cpp
Removed tabs everywhere except autogenerated & external files. Add make
2007-04-16 18:10:23 +00:00
SelectionDAG.cpp
fold noop vbitconvert instructions
2007-04-12 05:58:43 +00:00
SelectionDAGISel.cpp
disable switch lowering using shift/and. It still breaks ppc bootstrap for
2007-04-14 19:39:41 +00:00
SelectionDAGPrinter.cpp
Removing even more <iostream> includes.
2006-12-07 20:04:42 +00:00
TargetLowering.cpp
fix a pasto
2007-04-18 03:01:40 +00:00
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