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2f69e4cf32
There is an assert at line 558 in ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA).
This assert needs to addressed for post RA scheduler. Until that assert is addressed,
any passes that uses post ra scheduler will fail. So, I am temporarily disabling the
hexagon tests until that fix is in.
The assert is as follows:
assert(!MI->isTerminator() && !MI->isLabel() &&
"Cannot schedule terminators or labels!");
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154617 91177308-0d34-0410-b5e6-96231b3b80d8
24 lines
733 B
LLVM
24 lines
733 B
LLVM
; RUN: true
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; DISABLED: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
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; CHECK: __hexagon_addsf3
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; CHECK: __hexagon_subsf3
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define void @foo(float* %acc, float %num, float %num2) nounwind {
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entry:
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%acc.addr = alloca float*, align 4
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%num.addr = alloca float, align 4
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%num2.addr = alloca float, align 4
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store float* %acc, float** %acc.addr, align 4
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store float %num, float* %num.addr, align 4
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store float %num2, float* %num2.addr, align 4
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%0 = load float** %acc.addr, align 4
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%1 = load float* %0
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%2 = load float* %num.addr, align 4
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%add = fadd float %1, %2
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%3 = load float* %num2.addr, align 4
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%sub = fsub float %add, %3
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%4 = load float** %acc.addr, align 4
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store float %sub, float* %4
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ret void
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}
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