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06a6a300c5
intrinsics with target-indepdent intrinsics. The first instruction(s) to be handled are the vector versions of count leading zeros (ctlz). The changes here are to clang so that it generates a target independent vector ctlz when it sees an ARM dependent vector ctlz. The changes in llvm are to match the target independent vector ctlz and in VMCore/AutoUpgrade.cpp to update any existing bc files containing ARM dependent vector ctlzs with target-independent ctlzs. There are also changes to an existing test case in llvm for ARM vector count instructions and a new test for the bitcode upgrade. <rdar://problem/11831778> There is deliberately no test for the change to clang, as so far as I know, no consensus has been reached regarding how to test neon instructions in clang; q.v. <rdar://problem/8762292> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160200 91177308-0d34-0410-b5e6-96231b3b80d8
13 lines
450 B
LLVM
13 lines
450 B
LLVM
; RUN: llvm-as < %s | llvm-dis | FileCheck %s
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; NB: currently tests only vclz, should also test vcnt and vcls
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define <4 x i16> @vclz16(<4 x i16>* %A) nounwind {
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;CHECK: @vclz16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = call <4 x i16> @llvm.arm.neon.vclz.v4i16(<4 x i16> %tmp1)
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;CHECK: {{call.*@llvm.ctlz.v4i16\(<4 x i16>.*, i1 false}}
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ret <4 x i16> %tmp2
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}
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declare <4 x i16> @llvm.arm.neon.vclz.v4i16(<4 x i16>) nounwind readnone
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