Vincent Lejeune f3d6e32c09 R600: Add a pass that merge Vector Register ...

Previously commited @183279 but tests were failing, reverted @183286
It was broken because @183336 was missing, now it's there.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183343 91177308-0d34-0410-b5e6-96231b3b80d8

2013-06-05 21:38:04 +00:00

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AArch64

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ARM

Cortex-R5 can issue Thumb2 integer division instructions.

2013-06-04 22:52:09 +00:00

CPP

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Generic

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Hexagon

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Inputs

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MBlaze

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Mips

[mips] brcond + setgt/setugt instruction selection patterns.

2013-06-05 19:49:55 +00:00

MSP430

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NVPTX

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PowerPC

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R600

R600: Add a pass that merge Vector Register

2013-06-05 21:38:04 +00:00

SI

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SPARC

Sparc: Add support for indirect branch and blockaddress in Sparc backend.

2013-06-03 05:58:33 +00:00

SystemZ

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Thumb

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Thumb2

Cortex-R5 can issue Thumb2 integer division instructions.

2013-06-04 22:52:09 +00:00

X86

[PATCH] Fix VGATHER* operand constraints

2013-06-05 18:12:26 +00:00

XCore

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