Kay Tiong Khoo 6c3daabc3e Added 0x0D to 2-byte opcode extension table for prefetch* variants ... Fixed decode of existing 3dNow prefetchw instruction Intel is scheduled to add a compatible prefetchw (same encoding) to future CPUs git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174920 91177308-0d34-0410-b5e6-96231b3b80d8		2013-02-12 00:19:12 +00:00
..
AsmMatcherEmitter.cpp	Allow targets to add custom asm operand matching logic.	2013-02-06 06:00:06 +00:00
AsmWriterEmitter.cpp	This patch that sets the EmitAlias flag in td files	2013-02-05 08:32:10 +00:00
AsmWriterInst.cpp
AsmWriterInst.h
CallingConvEmitter.cpp
CMakeLists.txt
CodeEmitterGen.cpp
CodeGenDAGPatterns.cpp
CodeGenDAGPatterns.h
CodeGenInstruction.cpp
CodeGenInstruction.h
CodeGenIntrinsics.h
CodeGenMapTable.cpp
CodeGenRegisters.cpp	Clarify intent.	2013-01-31 17:56:23 +00:00
CodeGenRegisters.h
CodeGenSchedule.cpp	MachineModel: Inconsequential TableGen SubtargetEmitter fix.	2013-02-01 03:19:54 +00:00
CodeGenSchedule.h
CodeGenTarget.cpp
CodeGenTarget.h
DAGISelEmitter.cpp
DAGISelMatcher.cpp
DAGISelMatcher.h
DAGISelMatcherEmitter.cpp	Fix comments	2013-02-05 16:53:11 +00:00
DAGISelMatcherGen.cpp
DAGISelMatcherOpt.cpp
DFAPacketizerEmitter.cpp
DisassemblerEmitter.cpp
FastISelEmitter.cpp
FixedLenDecoderEmitter.cpp
InstrInfoEmitter.cpp
IntrinsicEmitter.cpp
LLVMBuild.txt
Makefile
OptParserEmitter.cpp
PseudoLoweringEmitter.cpp
RegisterInfoEmitter.cpp
SequenceToOffsetTable.h
SetTheory.cpp
SetTheory.h
StringToOffsetTable.h
SubtargetEmitter.cpp
TableGen.cpp
TableGenBackends.h
TGValueTypes.cpp
X86DisassemblerShared.h
X86DisassemblerTables.cpp
X86DisassemblerTables.h
X86ModRMFilters.cpp
X86ModRMFilters.h
X86RecognizableInstr.cpp	Added 0x0D to 2-byte opcode extension table for prefetch* variants	2013-02-12 00:19:12 +00:00
X86RecognizableInstr.h