Tim Northover 6c0138e5fc ARM: Use non-VFP softcalls on embedded Darwinish targets ... The compiler-rt functions __adddf3vfp and so on exist purely to allow Thumb1 code to make use of VFP instructions by switching back to ARM mode, they make no sense for M-class processors which don't even have an ARM mode. Given that justification, in practice this is a platform ABI decision so the actual check is based on that rather than CPU features. rdar://problem/15302004 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193327 91177308-0d34-0410-b5e6-96231b3b80d8		2013-10-24 10:37:09 +00:00
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AArch64	[AArch64] Fix NZCV reg live-in bug in F128CSEL codegen.	2013-10-24 08:28:24 +00:00
ARM	ARM: Use non-VFP softcalls on embedded Darwinish targets	2013-10-24 10:37:09 +00:00
CPP
Generic	Change objectsize intrinsic to accept different address spaces.	2013-10-07 18:06:48 +00:00
Hexagon
Inputs
Mips	[mips][msa] Added support for matching fexp2 from normal IR (i.e. not intrinsics)	2013-10-23 10:36:52 +00:00
MSP430	Make sure SP is always aligned on a 2 byte boundary	2013-10-24 09:32:31 +00:00
NVPTX	[NVPTX] Switch from StrongPHIElimination to PHIElimination in NVPTXTargetMachine, and add some missing optimization passes to addOptimizedRegAlloc	2013-10-11 12:39:39 +00:00
PowerPC	Update PPC loop tests after SCEV non-unit-stride checkin r193015.	2013-10-19 00:14:04 +00:00
R600	R600/SI: fix MIMG writemask adjustement	2013-10-23 02:53:47 +00:00
SPARC
SystemZ	Replace sra with srl if a single sign bit is required	2013-10-17 11:16:57 +00:00
Thumb	17309 ARM backend incorrectly lowers COPY_STRUCT_BYVAL_I32 for thumb1 targets	2013-10-17 19:52:05 +00:00
Thumb2	MachineSink: Fix and tweak critical-edge breaking heuristic.	2013-10-14 16:57:17 +00:00
X86	Added test for -elf configuration, to see that _alloca call is properly	2013-10-24 09:36:08 +00:00
XCore