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6c0138e5fc
The compiler-rt functions __adddf3vfp and so on exist purely to allow Thumb1 code to make use of VFP instructions by switching back to ARM mode, they make no sense for M-class processors which don't even have an ARM mode. Given that justification, in practice this is a platform ABI decision so the actual check is based on that rather than CPU features. rdar://problem/15302004 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193327 91177308-0d34-0410-b5e6-96231b3b80d8
23 lines
636 B
LLVM
23 lines
636 B
LLVM
; RUN: llc -mtriple=thumbv7m-apple-darwin-eabi -mcpu=cortex-m3 < %s | FileCheck %s --check-prefix=CHECK-M3
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; RUN: llc -mtriple=thumbv7em-apple-darwin-eabi -mcpu=cortex-m4 < %s | FileCheck %s --check-prefix=CHECK-M4
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define float @float_op(float %lhs, float %rhs) {
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%sum = fadd float %lhs, %rhs
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ret float %sum
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; CHECK-M3-LABEL: float_op:
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; CHECK-M3: blx ___addsf3
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; CHECK-M4-LABEL: float_op:
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; CHECK-M4: vadd.f32
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}
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define double @double_op(double %lhs, double %rhs) {
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%sum = fadd double %lhs, %rhs
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ret double %sum
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; CHECK-M3-LABEL: double_op:
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; CHECK-M3: blx ___adddf3
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; CHECK-M4-LABEL: double_op:
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; CHECK-M4: blx ___adddf3
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}
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