Matheus Almeida 6c71a5f6e4 [mips] Add instruction alias (sll and srl). ... Summary: The pattern sll/srl $rd, $rt, $rs is found in handwritten assembly which is just a shorthand version of sllv/srlv $rd, $rt, $rs. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3483 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207657 91177308-0d34-0410-b5e6-96231b3b80d8		2014-04-30 15:23:04 +00:00
..
AArch64	ARM64: enable AArch64's basic-a64-instructions test	2014-04-30 13:37:10 +00:00
ARM	ARM: print COFF function header for Windows on ARM	2014-04-30 06:14:25 +00:00
ARM64	ARM64: use 32-bit operations for uxtb & uxth	2014-04-30 13:37:02 +00:00
AsmParser	Integrated assbemler, macros: added 'vararg' argument qualifier support.	2014-04-23 06:56:28 +00:00
COFF	MC: duplicate .file test for WoA (SVN r207341)	2014-04-27 16:10:57 +00:00
Disassembler	ARM64: print lsr instead of lsrv for variable shifts (etc)	2014-04-30 13:37:07 +00:00
ELF	Add an option for evaluating past symbols.	2014-04-28 20:53:11 +00:00
MachO	Fix the assembler to print a better relocatable expression error	2014-04-22 17:27:29 +00:00
Markup
Mips	[mips] Add instruction alias (sll and srl).	2014-04-30 15:23:04 +00:00
PowerPC	[MC] Emit an error if cfi_startproc is used before a symbol is defined.	2014-04-15 01:17:45 +00:00
Sparc	[Sparc] Add trap on integer condition codes (Ticc) instructions to Sparc backend.	2014-03-02 23:39:07 +00:00
SystemZ	[SystemZ] Add support for z196 float<->unsigned conversions	2014-03-21 10:56:30 +00:00
X86	[AVX512] Implemented integer conversions up/down with masking.	2014-04-22 11:36:19 +00:00