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https://github.com/c64scene-ar/llvm-6502.git
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6dc4d8f0ed
We were passing the scratch buffer address to the shaders via user sgprs, but now we use external symbols and have the driver patch the shader using reloc information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226586 91177308-0d34-0410-b5e6-96231b3b80d8
456 lines
15 KiB
C++
456 lines
15 KiB
C++
//===-- SIRegisterInfo.cpp - SI Register Information ---------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief SI implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "SIRegisterInfo.h"
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#include "AMDGPUSubtarget.h"
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#include "SIInstrInfo.h"
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#include "SIMachineFunctionInfo.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/LLVMContext.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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SIRegisterInfo::SIRegisterInfo(const AMDGPUSubtarget &st)
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: AMDGPURegisterInfo(st)
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{ }
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BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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Reserved.set(AMDGPU::EXEC);
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// EXEC_LO and EXEC_HI could be allocated and used as regular register,
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// but this seems likely to result in bugs, so I'm marking them as reserved.
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Reserved.set(AMDGPU::EXEC_LO);
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Reserved.set(AMDGPU::EXEC_HI);
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Reserved.set(AMDGPU::INDIRECT_BASE_ADDR);
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Reserved.set(AMDGPU::FLAT_SCR);
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Reserved.set(AMDGPU::FLAT_SCR_LO);
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Reserved.set(AMDGPU::FLAT_SCR_HI);
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// Reserve some VGPRs to use as temp registers in case we have to spill VGPRs
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Reserved.set(AMDGPU::VGPR255);
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Reserved.set(AMDGPU::VGPR254);
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return Reserved;
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}
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unsigned SIRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
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MachineFunction &MF) const {
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return RC->getNumRegs();
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}
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bool SIRegisterInfo::requiresRegisterScavenging(const MachineFunction &Fn) const {
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return Fn.getFrameInfo()->hasStackObjects();
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}
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static unsigned getNumSubRegsForSpillOp(unsigned Op) {
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switch (Op) {
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case AMDGPU::SI_SPILL_S512_SAVE:
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case AMDGPU::SI_SPILL_S512_RESTORE:
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case AMDGPU::SI_SPILL_V512_SAVE:
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case AMDGPU::SI_SPILL_V512_RESTORE:
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return 16;
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case AMDGPU::SI_SPILL_S256_SAVE:
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case AMDGPU::SI_SPILL_S256_RESTORE:
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case AMDGPU::SI_SPILL_V256_SAVE:
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case AMDGPU::SI_SPILL_V256_RESTORE:
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return 8;
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case AMDGPU::SI_SPILL_S128_SAVE:
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case AMDGPU::SI_SPILL_S128_RESTORE:
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case AMDGPU::SI_SPILL_V128_SAVE:
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case AMDGPU::SI_SPILL_V128_RESTORE:
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return 4;
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case AMDGPU::SI_SPILL_V96_SAVE:
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case AMDGPU::SI_SPILL_V96_RESTORE:
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return 3;
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case AMDGPU::SI_SPILL_S64_SAVE:
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case AMDGPU::SI_SPILL_S64_RESTORE:
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case AMDGPU::SI_SPILL_V64_SAVE:
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case AMDGPU::SI_SPILL_V64_RESTORE:
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return 2;
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case AMDGPU::SI_SPILL_S32_SAVE:
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case AMDGPU::SI_SPILL_S32_RESTORE:
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case AMDGPU::SI_SPILL_V32_SAVE:
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case AMDGPU::SI_SPILL_V32_RESTORE:
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return 1;
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default: llvm_unreachable("Invalid spill opcode");
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}
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}
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void SIRegisterInfo::buildScratchLoadStore(MachineBasicBlock::iterator MI,
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unsigned LoadStoreOp,
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unsigned Value,
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unsigned ScratchRsrcReg,
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unsigned ScratchOffset,
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int64_t Offset,
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RegScavenger *RS) const {
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const SIInstrInfo *TII = static_cast<const SIInstrInfo*>(ST.getInstrInfo());
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MachineBasicBlock *MBB = MI->getParent();
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const MachineFunction *MF = MI->getParent()->getParent();
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LLVMContext &Ctx = MF->getFunction()->getContext();
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DebugLoc DL = MI->getDebugLoc();
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bool IsLoad = TII->get(LoadStoreOp).mayLoad();
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bool RanOutOfSGPRs = false;
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unsigned SOffset = ScratchOffset;
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unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
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unsigned Size = NumSubRegs * 4;
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if (!isUInt<12>(Offset + Size)) {
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dbgs() << "Offset scavenge\n";
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SOffset = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, MI, 0);
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if (SOffset == AMDGPU::NoRegister) {
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RanOutOfSGPRs = true;
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SOffset = AMDGPU::SGPR0;
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}
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BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_ADD_U32), SOffset)
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.addReg(ScratchOffset)
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.addImm(Offset);
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Offset = 0;
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}
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if (RanOutOfSGPRs)
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Ctx.emitError("Ran out of SGPRs for spilling VGPRS");
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for (unsigned i = 0, e = NumSubRegs; i != e; ++i, Offset += 4) {
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unsigned SubReg = NumSubRegs > 1 ?
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getPhysRegSubReg(Value, &AMDGPU::VGPR_32RegClass, i) :
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Value;
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bool IsKill = (i == e - 1);
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BuildMI(*MBB, MI, DL, TII->get(LoadStoreOp))
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.addReg(SubReg, getDefRegState(IsLoad))
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.addReg(ScratchRsrcReg, getKillRegState(IsKill))
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.addImm(Offset)
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.addReg(SOffset, getKillRegState(IsKill))
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.addImm(0) // glc
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.addImm(0) // slc
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.addImm(0) // tfe
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.addReg(Value, RegState::Implicit | getDefRegState(IsLoad));
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}
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}
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void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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int SPAdj, unsigned FIOperandNum,
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RegScavenger *RS) const {
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MachineFunction *MF = MI->getParent()->getParent();
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MachineBasicBlock *MBB = MI->getParent();
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SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
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MachineFrameInfo *FrameInfo = MF->getFrameInfo();
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const SIInstrInfo *TII = static_cast<const SIInstrInfo*>(ST.getInstrInfo());
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DebugLoc DL = MI->getDebugLoc();
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MachineOperand &FIOp = MI->getOperand(FIOperandNum);
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int Index = MI->getOperand(FIOperandNum).getIndex();
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switch (MI->getOpcode()) {
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// SGPR register spill
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case AMDGPU::SI_SPILL_S512_SAVE:
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case AMDGPU::SI_SPILL_S256_SAVE:
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case AMDGPU::SI_SPILL_S128_SAVE:
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case AMDGPU::SI_SPILL_S64_SAVE:
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case AMDGPU::SI_SPILL_S32_SAVE: {
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unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
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for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
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unsigned SubReg = getPhysRegSubReg(MI->getOperand(0).getReg(),
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&AMDGPU::SGPR_32RegClass, i);
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struct SIMachineFunctionInfo::SpilledReg Spill =
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MFI->getSpilledReg(MF, Index, i);
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if (Spill.VGPR == AMDGPU::NoRegister) {
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LLVMContext &Ctx = MF->getFunction()->getContext();
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Ctx.emitError("Ran out of VGPRs for spilling SGPR");
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}
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BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_WRITELANE_B32), Spill.VGPR)
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.addReg(SubReg)
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.addImm(Spill.Lane);
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}
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MI->eraseFromParent();
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break;
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}
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// SGPR register restore
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case AMDGPU::SI_SPILL_S512_RESTORE:
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case AMDGPU::SI_SPILL_S256_RESTORE:
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case AMDGPU::SI_SPILL_S128_RESTORE:
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case AMDGPU::SI_SPILL_S64_RESTORE:
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case AMDGPU::SI_SPILL_S32_RESTORE: {
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unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
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for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
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unsigned SubReg = getPhysRegSubReg(MI->getOperand(0).getReg(),
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&AMDGPU::SGPR_32RegClass, i);
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bool isM0 = SubReg == AMDGPU::M0;
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struct SIMachineFunctionInfo::SpilledReg Spill =
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MFI->getSpilledReg(MF, Index, i);
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if (Spill.VGPR == AMDGPU::NoRegister) {
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LLVMContext &Ctx = MF->getFunction()->getContext();
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Ctx.emitError("Ran out of VGPRs for spilling SGPR");
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}
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if (isM0) {
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dbgs() << "Scavenge M0\n";
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SubReg = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, MI, 0);
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}
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BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_READLANE_B32), SubReg)
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.addReg(Spill.VGPR)
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.addImm(Spill.Lane)
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.addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine);
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if (isM0) {
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BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
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.addReg(SubReg);
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}
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}
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TII->insertNOPs(MI, 3);
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MI->eraseFromParent();
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break;
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}
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// VGPR register spill
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case AMDGPU::SI_SPILL_V512_SAVE:
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case AMDGPU::SI_SPILL_V256_SAVE:
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case AMDGPU::SI_SPILL_V128_SAVE:
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case AMDGPU::SI_SPILL_V96_SAVE:
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case AMDGPU::SI_SPILL_V64_SAVE:
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case AMDGPU::SI_SPILL_V32_SAVE:
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buildScratchLoadStore(MI, AMDGPU::BUFFER_STORE_DWORD_OFFSET,
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TII->getNamedOperand(*MI, AMDGPU::OpName::src)->getReg(),
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TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_rsrc)->getReg(),
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TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_offset)->getReg(),
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FrameInfo->getObjectOffset(Index), RS);
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MI->eraseFromParent();
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break;
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case AMDGPU::SI_SPILL_V32_RESTORE:
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case AMDGPU::SI_SPILL_V64_RESTORE:
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case AMDGPU::SI_SPILL_V128_RESTORE:
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case AMDGPU::SI_SPILL_V256_RESTORE:
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case AMDGPU::SI_SPILL_V512_RESTORE: {
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buildScratchLoadStore(MI, AMDGPU::BUFFER_LOAD_DWORD_OFFSET,
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TII->getNamedOperand(*MI, AMDGPU::OpName::dst)->getReg(),
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TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_rsrc)->getReg(),
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TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_offset)->getReg(),
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FrameInfo->getObjectOffset(Index), RS);
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MI->eraseFromParent();
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break;
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}
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default: {
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int64_t Offset = FrameInfo->getObjectOffset(Index);
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FIOp.ChangeToImmediate(Offset);
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if (!TII->isImmOperandLegal(MI, FIOperandNum, FIOp)) {
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unsigned TmpReg = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, SPAdj);
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BuildMI(*MBB, MI, MI->getDebugLoc(),
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TII->get(AMDGPU::V_MOV_B32_e32), TmpReg)
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.addImm(Offset);
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FIOp.ChangeToRegister(TmpReg, false, false, true);
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}
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}
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}
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}
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const TargetRegisterClass * SIRegisterInfo::getCFGStructurizerRegClass(
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MVT VT) const {
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switch(VT.SimpleTy) {
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default:
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case MVT::i32: return &AMDGPU::VGPR_32RegClass;
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}
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}
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unsigned SIRegisterInfo::getHWRegIndex(unsigned Reg) const {
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return getEncodingValue(Reg) & 0xff;
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}
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const TargetRegisterClass *SIRegisterInfo::getPhysRegClass(unsigned Reg) const {
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assert(!TargetRegisterInfo::isVirtualRegister(Reg));
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static const TargetRegisterClass *BaseClasses[] = {
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&AMDGPU::VGPR_32RegClass,
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&AMDGPU::SReg_32RegClass,
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&AMDGPU::VReg_64RegClass,
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&AMDGPU::SReg_64RegClass,
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&AMDGPU::VReg_96RegClass,
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&AMDGPU::VReg_128RegClass,
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&AMDGPU::SReg_128RegClass,
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&AMDGPU::VReg_256RegClass,
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&AMDGPU::SReg_256RegClass,
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&AMDGPU::VReg_512RegClass
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};
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for (const TargetRegisterClass *BaseClass : BaseClasses) {
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if (BaseClass->contains(Reg)) {
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return BaseClass;
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}
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}
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return nullptr;
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}
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bool SIRegisterInfo::hasVGPRs(const TargetRegisterClass *RC) const {
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return getCommonSubClass(&AMDGPU::VGPR_32RegClass, RC) ||
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getCommonSubClass(&AMDGPU::VReg_64RegClass, RC) ||
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getCommonSubClass(&AMDGPU::VReg_96RegClass, RC) ||
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getCommonSubClass(&AMDGPU::VReg_128RegClass, RC) ||
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getCommonSubClass(&AMDGPU::VReg_256RegClass, RC) ||
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getCommonSubClass(&AMDGPU::VReg_512RegClass, RC);
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}
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const TargetRegisterClass *SIRegisterInfo::getEquivalentVGPRClass(
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const TargetRegisterClass *SRC) const {
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if (hasVGPRs(SRC)) {
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return SRC;
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} else if (SRC == &AMDGPU::SCCRegRegClass) {
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return &AMDGPU::VCCRegRegClass;
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} else if (getCommonSubClass(SRC, &AMDGPU::SGPR_32RegClass)) {
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return &AMDGPU::VGPR_32RegClass;
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} else if (getCommonSubClass(SRC, &AMDGPU::SGPR_64RegClass)) {
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return &AMDGPU::VReg_64RegClass;
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} else if (getCommonSubClass(SRC, &AMDGPU::SReg_128RegClass)) {
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return &AMDGPU::VReg_128RegClass;
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} else if (getCommonSubClass(SRC, &AMDGPU::SReg_256RegClass)) {
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return &AMDGPU::VReg_256RegClass;
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} else if (getCommonSubClass(SRC, &AMDGPU::SReg_512RegClass)) {
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return &AMDGPU::VReg_512RegClass;
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}
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return nullptr;
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}
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const TargetRegisterClass *SIRegisterInfo::getSubRegClass(
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const TargetRegisterClass *RC, unsigned SubIdx) const {
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if (SubIdx == AMDGPU::NoSubRegister)
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return RC;
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// If this register has a sub-register, we can safely assume it is a 32-bit
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// register, because all of SI's sub-registers are 32-bit.
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if (isSGPRClass(RC)) {
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return &AMDGPU::SGPR_32RegClass;
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} else {
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return &AMDGPU::VGPR_32RegClass;
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}
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}
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unsigned SIRegisterInfo::getPhysRegSubReg(unsigned Reg,
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const TargetRegisterClass *SubRC,
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unsigned Channel) const {
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switch (Reg) {
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case AMDGPU::VCC:
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switch(Channel) {
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case 0: return AMDGPU::VCC_LO;
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case 1: return AMDGPU::VCC_HI;
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default: llvm_unreachable("Invalid SubIdx for VCC");
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}
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case AMDGPU::FLAT_SCR:
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switch (Channel) {
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case 0:
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return AMDGPU::FLAT_SCR_LO;
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case 1:
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return AMDGPU::FLAT_SCR_HI;
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default:
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llvm_unreachable("Invalid SubIdx for FLAT_SCR");
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}
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break;
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case AMDGPU::EXEC:
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switch (Channel) {
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case 0:
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return AMDGPU::EXEC_LO;
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case 1:
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return AMDGPU::EXEC_HI;
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default:
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llvm_unreachable("Invalid SubIdx for EXEC");
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}
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break;
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}
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const TargetRegisterClass *RC = getPhysRegClass(Reg);
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// 32-bit registers don't have sub-registers, so we can just return the
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// Reg. We need to have this check here, because the calculation below
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// using getHWRegIndex() will fail with special 32-bit registers like
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// VCC_LO, VCC_HI, EXEC_LO, EXEC_HI and M0.
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if (RC->getSize() == 4) {
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assert(Channel == 0);
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return Reg;
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}
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unsigned Index = getHWRegIndex(Reg);
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return SubRC->getRegister(Index + Channel);
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}
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bool SIRegisterInfo::opCanUseLiteralConstant(unsigned OpType) const {
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return OpType == AMDGPU::OPERAND_REG_IMM32;
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}
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bool SIRegisterInfo::opCanUseInlineConstant(unsigned OpType) const {
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if (opCanUseLiteralConstant(OpType))
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return true;
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return OpType == AMDGPU::OPERAND_REG_INLINE_C;
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}
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unsigned SIRegisterInfo::getPreloadedValue(const MachineFunction &MF,
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enum PreloadedValue Value) const {
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const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
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switch (Value) {
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case SIRegisterInfo::TGID_X:
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return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 0);
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case SIRegisterInfo::TGID_Y:
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return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 1);
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case SIRegisterInfo::TGID_Z:
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return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 2);
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case SIRegisterInfo::SCRATCH_WAVE_OFFSET:
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return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 4);
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case SIRegisterInfo::SCRATCH_PTR:
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return AMDGPU::SGPR2_SGPR3;
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case SIRegisterInfo::INPUT_PTR:
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return AMDGPU::SGPR0_SGPR1;
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case SIRegisterInfo::TIDIG_X:
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return AMDGPU::VGPR0;
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case SIRegisterInfo::TIDIG_Y:
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return AMDGPU::VGPR1;
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case SIRegisterInfo::TIDIG_Z:
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return AMDGPU::VGPR2;
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}
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llvm_unreachable("unexpected preloaded value type");
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}
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/// \brief Returns a register that is not used at any point in the function.
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/// If all registers are used, then this function will return
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// AMDGPU::NoRegister.
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unsigned SIRegisterInfo::findUnusedRegister(const MachineRegisterInfo &MRI,
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const TargetRegisterClass *RC) const {
|
|
|
|
for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
|
|
I != E; ++I) {
|
|
if (!MRI.isPhysRegUsed(*I))
|
|
return *I;
|
|
}
|
|
return AMDGPU::NoRegister;
|
|
}
|
|
|