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https://github.com/c64scene-ar/llvm-6502.git
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e3e5fcab94
This is a 1-line patch (with a TODO for AVX because that will affect even more regression tests) that lets us substitute the appropriate 64-bit store for the float/double/int domains. It's not clear to me exactly what the difference is between the 0xD6 (MOVPQI2QImr) and 0x7E (MOVSDto64mr) opcodes, but this is apparently the right choice. Differential Revision: http://reviews.llvm.org/D8691 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235014 91177308-0d34-0410-b5e6-96231b3b80d8
59 lines
1.7 KiB
LLVM
59 lines
1.7 KiB
LLVM
; RUN: llc < %s -mtriple=i686-darwin -mattr=+mmx,+sse2 | FileCheck %s -check-prefix=X86-32
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; RUN: llc < %s -mtriple=x86_64-darwin -mattr=+mmx,+sse4.1 | FileCheck %s -check-prefix=X86-64
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; This is not an MMX operation; promoted to XMM.
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define x86_mmx @t0(i32 %A) nounwind {
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; X86-32-LABEL: t0:
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; X86-32: ## BB#0:
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; X86-32: movd {{[0-9]+}}(%esp), %xmm0
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; X86-32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,0,1,1]
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; X86-32-NEXT: movq %xmm0, (%esp)
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; X86-32-NEXT: movq (%esp), %mm0
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; X86-32-NEXT: addl $12, %esp
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; X86-32-NEXT: retl
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%tmp3 = insertelement <2 x i32> < i32 0, i32 undef >, i32 %A, i32 1
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%tmp4 = bitcast <2 x i32> %tmp3 to x86_mmx
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ret x86_mmx %tmp4
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}
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define <8 x i8> @t1(i8 zeroext %x) nounwind {
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; X86-32-LABEL: t1:
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; X86-32: ## BB#0:
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; X86-32-NOT: movl
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; X86-32-NEXT: movd {{[0-9]+}}(%esp), %xmm0
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; X86-32-NEXT: retl
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%r = insertelement <8 x i8> undef, i8 %x, i32 0
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ret <8 x i8> %r
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}
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; PR2574
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define <2 x float> @t2(<2 x float> %a0) {
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; X86-32-LABEL: t2:
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; X86-32: ## BB#0:
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; X86-32-NEXT: xorps %xmm0, %xmm0
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; X86-32-NEXT: retl
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%v1 = insertelement <2 x float> %a0, float 0.000000e+00, i32 0
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%v2 = insertelement <2 x float> %v1, float 0.000000e+00, i32 1
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ret <2 x float> %v2
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}
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@g0 = external global i16
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@g1 = external global <4 x i16>
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; PR2562
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define void @t3() {
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; X86-64-LABEL: t3:
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; X86-64: ## BB#0:
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; X86-64: pmovzxwd (%rcx)
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; X86-64-NEXT: movzwl
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; X86-64-NEXT: pinsrd $0
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; X86-64-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
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; X86-64-NEXT: movq %xmm0
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; X86-64-NEXT: retq
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load i16, i16* @g0
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load <4 x i16>, <4 x i16>* @g1
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insertelement <4 x i16> %2, i16 %1, i32 0
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store <4 x i16> %3, <4 x i16>* @g1
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ret void
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}
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