Evan Cheng 9d709a8edb Enable machine cse of instructions which define physical registers. ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105308 91177308-0d34-0410-b5e6-96231b3b80d8

2010-06-02 01:08:27 +00:00

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Alpha

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ARM

Enable machine cse of instructions which define physical registers.

2010-06-02 01:08:27 +00:00

Blackfin

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CBackend

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CellSPU

Fix handling of 'load' nodes.

2010-06-01 13:34:47 +00:00

CPP

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Generic

Enable a bunch more -regalloc=fast tests

2010-05-12 00:11:24 +00:00

MBlaze

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Mips

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MSP430

Insert ANY_EXTEND node instead of invalid truncate during DAG Combining (X & 1),

2010-05-01 12:52:34 +00:00

PIC16

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PowerPC

Fix some latency computation bugs: if the use is not a machine opcode do not just return zero.

2010-05-28 23:26:21 +00:00

SPARC

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SystemZ

SystemZ really does mean "has calls" and not just "adjusts stack." Go ahead and

2010-05-14 22:17:42 +00:00

Thumb

Enable a bunch more -regalloc=fast tests

2010-05-12 00:11:24 +00:00

Thumb2

Thumb2 RSBS instructions were being printed without the 'S' suffix.

2010-05-24 18:44:06 +00:00

X86

Fill in missing support for ISD::FEXP, ISD::FPOWI, and friends.

2010-06-01 18:35:14 +00:00

XCore

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