llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-10 02:36:06 +00:00

History

Daniel Sanders 6ff1ef9931 [mips][msa] Added support for matching bins[lr]i.[bhwd] from normal IR (i.e. not intrinsics)

This required correcting the definition of the bins[lr]i intrinsics because
the result is also the first operand.

It also required removing the (arbitrary) check for 32-bit immediates in
MipsSEDAGToDAGISel::selectVSplat().

Currently using binsli.d with 2 bits set in the mask doesn't select binsli.d
because the constant is legalized into a ConstantPool. Similar things can
happen with binsri.d with more than 10 bits set in the mask. The resulting
code when this happens is correct but not optimal.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193687 91177308-0d34-0410-b5e6-96231b3b80d8

2013-10-30 14:45:14 +00:00

Analysis

SCEV: Make the final add of an inbounds GEP nuw if we know that the index is positive.

2013-10-28 07:30:06 +00:00

AsmParser

Revert r193251 : Use address-taken to disambiguate global variable and indirect memops.

2013-10-27 03:08:44 +00:00

Bitcode

Revert r193251 : Use address-taken to disambiguate global variable and indirect memops.

2013-10-27 03:08:44 +00:00

CodeGen

Revert "SelectionDAG: Teach the legalizer to split SETCC if VSELECT needs splitting too."