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https://github.com/c64scene-ar/llvm-6502.git
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6ad251358e
def : Pat<(X86Movss VR128:$src1,
(bc_v4i32 (v2i64 (load addr:$src2)))),
(MOVLPSrm VR128:$src1, addr:$src2)>;
This matches a MOVSS dag with a MOVLPS instruction. However, MOVSS will replace only the low 32 bits of the register, while the MOVLPS instruction will replace the low 64 bits. A testcase is added and illustrates the bug and also modified the one that was already present. Patch by Tanya Lattner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137227 91177308-0d34-0410-b5e6-96231b3b80d8
46 lines
1.7 KiB
LLVM
46 lines
1.7 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s
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; RUN: llc -O0 < %s -march=x86 -mcpu=core2 | FileCheck %s --check-prefix=CHECK_O0
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define <4 x i32> @t00(<4 x i32>* %a0) nounwind ssp {
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entry:
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; CHECK: movaps ({{%rdi|%rcx}}), %xmm0
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; CHECK: movaps %xmm0, %xmm1
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; CHECK-NEXT: movss %xmm2, %xmm1
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; CHECK-NEXT: shufps $36, %xmm1, %xmm0
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%0 = load <4 x i32>* undef, align 16
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%1 = load <4 x i32>* %a0, align 16
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%2 = shufflevector <4 x i32> %1, <4 x i32> %0, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
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ret <4 x i32> %2
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}
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define void @t01(double* %a0) nounwind ssp {
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entry:
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; CHECK_O0: movsd (%eax), %xmm0
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; CHECK_O0: unpcklpd %xmm0, %xmm0
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%tmp93 = load double* %a0, align 8
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%vecinit94 = insertelement <2 x double> undef, double %tmp93, i32 1
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store <2 x double> %vecinit94, <2 x double>* undef
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ret void
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}
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define void @t02(<8 x i32>* %source, <2 x i32>* %dest) nounwind noinline {
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entry:
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; CHECK: movaps 32({{%rdi|%rcx}}), %xmm0
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; CHECK-NEXT: movaps 48({{%rdi|%rcx}}), %xmm1
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; CHECK-NEXT: movss %xmm1, %xmm0
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; CHECK-NEXT: movq %xmm0, ({{%rsi|%rdx}})
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%0 = bitcast <8 x i32>* %source to <4 x i32>*
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%arrayidx = getelementptr inbounds <4 x i32>* %0, i64 3
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%tmp2 = load <4 x i32>* %arrayidx, align 16
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%tmp3 = extractelement <4 x i32> %tmp2, i32 0
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%tmp5 = insertelement <2 x i32> <i32 undef, i32 0>, i32 %tmp3, i32 0
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%arrayidx7 = getelementptr inbounds <8 x i32>* %source, i64 1
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%1 = bitcast <8 x i32>* %arrayidx7 to <4 x i32>*
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%tmp8 = load <4 x i32>* %1, align 16
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%tmp9 = extractelement <4 x i32> %tmp8, i32 1
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%tmp11 = insertelement <2 x i32> %tmp5, i32 %tmp9, i32 1
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store <2 x i32> %tmp11, <2 x i32>* %dest, align 8
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ret void
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}
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