Bill Wendling 70fcb6bf58 CellSPU doesn't appear to support fully the "ISD::ROTR" operation. The DAG ...

combiner can now generate ROTR if the backend says that it can handle it. Cell
SPU says this, but gets an error from code gen saying that it can't select
ROTR. I'm xfailing this test until this can be fixed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55579 91177308-0d34-0410-b5e6-96231b3b80d8

2008-08-31 02:32:12 +00:00

..

Alpha

allow this to pass.

2008-08-29 17:18:26 +00:00

ARM

…

CBackend

…

CellSPU

CellSPU doesn't appear to support fully the "ISD::ROTR" operation. The DAG

2008-08-31 02:32:12 +00:00

CPP

…

Generic

Improve support for vector casts in LLVM IR and CodeGen.

2008-08-14 20:04:46 +00:00

IA64

…

Mips

…

PowerPC

Testcases for ppc atomics.

2008-08-30 00:54:31 +00:00

SPARC

…

X86

Re-apply 55467 with fix. If copy is being replaced by remat'ed def, transfer the implicit defs onto the remat'ed instruction.

2008-08-30 09:09:33 +00:00