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On Nehalem and newer CPUs there is a 2 cycle latency penalty on using a register in a different domain than where it was defined. Some instructions have equvivalents for different domains, like por/orps/orpd. The SSEDomainFix pass tries to minimize the number of domain crossings by changing between equvivalent opcodes where possible. This is a work in progress, in particular the pass doesn't do anything yet. SSE instructions are tagged with their execution domain in TableGen using the last two bits of TSFlags. Note that not all instructions are tagged correctly. Life just isn't that simple. The SSE execution domain issue is very similar to the ARM NEON/VFP pipeline issue handled by NEONMoveFixPass. This pass may become target independent to handle both. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99524 91177308-0d34-0410-b5e6-96231b3b80d8
99 lines
3.0 KiB
C++
99 lines
3.0 KiB
C++
//===- SSEDomainFix.cpp - Use proper int/float domain for SSE ---*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the SSEDomainFix pass.
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//
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// Some SSE instructions like mov, and, or, xor are available in different
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// variants for different operand types. These variant instructions are
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// equivalent, but on Nehalem and newer cpus there is extra latency
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// transferring data between integer and floating point domains.
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//
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// This pass changes the variant instructions to minimize domain crossings.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "sse-domain-fix"
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#include "X86InstrInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/ADT/DepthFirstIterator.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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namespace {
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class SSEDomainFixPass : public MachineFunctionPass {
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static char ID;
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const X86InstrInfo *TII;
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MachineFunction *MF;
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MachineBasicBlock *MBB;
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public:
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SSEDomainFixPass() : MachineFunctionPass(&ID) {}
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesAll();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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virtual bool runOnMachineFunction(MachineFunction &MF);
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virtual const char *getPassName() const {
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return "SSE execution domain fixup";
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}
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private:
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void enterBasicBlock(MachineBasicBlock *MBB);
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};
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}
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char SSEDomainFixPass::ID = 0;
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void SSEDomainFixPass::enterBasicBlock(MachineBasicBlock *mbb) {
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MBB = mbb;
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DEBUG(dbgs() << "Entering MBB " << MBB->getName() << "\n");
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}
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bool SSEDomainFixPass::runOnMachineFunction(MachineFunction &mf) {
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MF = &mf;
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TII = static_cast<const X86InstrInfo*>(MF->getTarget().getInstrInfo());
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// If no XMM registers are used in the function, we can skip it completely.
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bool XMMIsUsed = false;
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for (TargetRegisterClass::const_iterator I = X86::VR128RegClass.begin(),
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E = X86::VR128RegClass.end(); I != E; ++I)
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if (MF->getRegInfo().isPhysRegUsed(*I)) {
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XMMIsUsed = true;
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break;
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}
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if (!XMMIsUsed) return false;
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MachineBasicBlock *Entry = MF->begin();
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SmallPtrSet<MachineBasicBlock*, 16> Visited;
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for (df_ext_iterator<MachineBasicBlock*,
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SmallPtrSet<MachineBasicBlock*, 16> >
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DFI = df_ext_begin(Entry, Visited), DFE = df_ext_end(Entry, Visited);
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DFI != DFE; ++DFI) {
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enterBasicBlock(*DFI);
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for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E;
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++I) {
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MachineInstr *MI = I;
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const unsigned *equiv = 0;
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X86InstrInfo::SSEDomain domain = TII->GetSSEDomain(MI, equiv);
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DEBUG(dbgs() << "-isd"[domain] << (equiv ? "* " : " ") << *MI);
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}
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}
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return false;
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}
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FunctionPass *llvm::createSSEDomainFixPass() {
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return new SSEDomainFixPass();
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}
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