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arm-tests.txt
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Simplify printing of ARM shifted immediates.
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2011-07-11 16:48:36 +00:00 |
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dg.exp
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invalid-Bcc-thumb.txt
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A8.6.16 B
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2011-04-12 00:14:49 +00:00 |
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invalid-BFI-arm.txt
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Add sanity checking for bad register specifier(s) for the DPFrm instructions.
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2011-04-08 00:29:09 +00:00 |
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invalid-CPS2p-arm.txt
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Also need to handle invalid imod values for CPS2p.
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2011-03-25 17:03:12 +00:00 |
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invalid-CPS3p-arm.txt
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Plug a leak in the arm disassembler and put the tests back.
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2011-03-24 21:14:28 +00:00 |
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invalid-DMB-thumb.txt
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Sanity check the option operand for DMB/DSB.
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2011-04-08 19:18:07 +00:00 |
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invalid-DSB-arm.txt
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Sanity check the option operand for DMB/DSB.
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2011-04-08 19:18:07 +00:00 |
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invalid-LDC-form-arm.txt
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Add a test case for a malformed LDC/LDC2 instructions with PUDW = 0b0000, which
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2011-03-31 20:54:30 +00:00 |
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invalid-LDR_POST-arm.txt
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Check invalid register encodings for LdFrm/StFrm ARM instructions and flag them as
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2011-04-11 18:34:12 +00:00 |
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invalid-LDR_PRE-arm.txt
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Check invalid register encodings for LdFrm/StFrm ARM instructions and flag them as
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2011-04-11 18:34:12 +00:00 |
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invalid-LDRB_POST-arm.txt
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Check invalid register encodings for LdFrm/StFrm ARM instructions and flag them as
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2011-04-11 18:34:12 +00:00 |
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invalid-LDRD_PRE-thumb.txt
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Add sanity check for Ld/St Dual forms of Thumb2 instructions.
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2011-04-12 23:31:00 +00:00 |
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invalid-LDRrs-arm.txt
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Fix single word and unsigned byte data transfer instruction encodings so that
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2011-03-31 19:28:35 +00:00 |
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invalid-LDRT-arm.txt
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Fix a LDRT/LDRBT decoding bug where for Encoding A2, if Inst{4} != 0, we should reject the instruction
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2011-04-01 20:21:38 +00:00 |
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invalid-LSL-regform.txt
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Add some more comments about checkings of invalid register numbers.
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2011-04-07 18:33:19 +00:00 |
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invalid-MCR-arm.txt
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A8.6.92 MCR (Encoding A1): if coproc == '101x' then SEE "Advanced SIMD and VFP"
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2011-04-06 20:49:02 +00:00 |
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invalid-MOVr-arm.txt
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Fixed MOVr for "should be" encoding bits for Inst{19-16} = 0b0000.
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2011-04-01 23:30:25 +00:00 |
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invalid-MOVs-arm.txt
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MOVs should have Inst{19-16} as 0b0000, otherwise, the instruction is UNPREDICTABLE.
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2011-04-01 23:15:50 +00:00 |
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invalid-MOVs-LSL-arm.txt
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ARM disassembler was erroneously accepting an invalid LSL instruction.
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2011-04-05 21:49:44 +00:00 |
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invalid-MOVTi16-arm.txt
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MOVi16 and MOVTi16 does not allow pc as the dest register, while MOVi allows it.
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2011-04-08 17:29:58 +00:00 |
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invalid-MSRi-arm.txt
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Sanity check MSRi for invalid mask values and reject it as invalid.
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2011-04-07 01:37:34 +00:00 |
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invalid-RFEorLDMIA-arm.txt
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Fix SRS/SRSW encoding bits.
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2011-04-05 00:16:18 +00:00 |
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invalid-RSC-arm.txt
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ARM disassembler was erroneously accepting an invalid RSC instruction.
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2011-04-05 22:18:07 +00:00 |
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invalid-SBFX-arm.txt
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Add sanity checking for bad register specifier(s) for the DPFrm instructions.
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2011-04-08 00:29:09 +00:00 |
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invalid-SMLAD-arm.txt
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Should also check SMLAD for invalid register values.
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2011-04-07 00:50:25 +00:00 |
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invalid-SRS-arm.txt
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Fix SRS/SRSW encoding bits.
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2011-04-05 00:16:18 +00:00 |
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invalid-SSAT-arm.txt
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Add sanity checking for invalid register encodings for saturating instructions.
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2011-04-07 19:02:08 +00:00 |
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invalid-STMIA_UPD-thumb.txt
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Print out a debug message when the reglist fails the sanity check for Thumb Ld/St Multiple.
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2011-04-12 17:09:04 +00:00 |
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invalid-STRBrs-arm.txt
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Check invalid register encodings for LdFrm/StFrm ARM instructions and flag them as
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2011-04-11 18:34:12 +00:00 |
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invalid-SXTB-arm.txt
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Add sanity checking for invalid register encodings for signed/unsigned extend instructions.
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2011-04-07 19:28:58 +00:00 |
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invalid-t2Bcc-thumb.txt
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Check for unallocated instruction encodings when disassembling Thumb Branch instructions (tBcc and t2Bcc).
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2011-04-13 21:35:49 +00:00 |
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invalid-t2LDRBT-thumb.txt
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The LDR*T/STR*T (unpriviledged load/store) operations don't take SP or PC as Rt.
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2011-04-13 21:04:32 +00:00 |
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invalid-t2LDREXD-thumb.txt
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Add sanity checkings for Thumb2 Load/Store Register Exclusive family of operations.
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2011-04-14 19:13:28 +00:00 |
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invalid-t2LDRSHi8-thumb.txt
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Check the corner cases for t2LDRSHi12 correctly and mark invalid encodings as such.
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2011-04-13 19:46:05 +00:00 |
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invalid-t2LDRSHi12-thumb.txt
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Check the corner cases for t2LDRSHi12 correctly and mark invalid encodings as such.
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2011-04-13 19:46:05 +00:00 |
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invalid-t2STR_POST-thumb.txt
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Add bad register checks for Thumb2 Ld/St instructions.
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2011-04-12 21:17:51 +00:00 |
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invalid-t2STRD_PRE-thumb.txt
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Add sanity check for Ld/St Dual forms of Thumb2 instructions.
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2011-04-12 23:31:00 +00:00 |
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invalid-t2STREXB-thumb.txt
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Add sanity checkings for Thumb2 Load/Store Register Exclusive family of operations.
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2011-04-14 19:13:28 +00:00 |
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invalid-t2STREXD-thumb.txt
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Add sanity checkings for Thumb2 Load/Store Register Exclusive family of operations.
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2011-04-14 19:13:28 +00:00 |
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invalid-UMAAL-arm.txt
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Check for invalid register encodings for UMAAL and friends where:
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2011-04-05 17:43:10 +00:00 |
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invalid-UQADD8-arm.txt
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Add sanity checking for bad register specifier(s) for the DPFrm instructions.
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2011-04-08 00:29:09 +00:00 |
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invalid-VLD1DUPq8_UPD-arm.txt
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The ARM disassembler did not handle the alignment correctly for VLD*DUP* instructions
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2011-04-15 00:10:45 +00:00 |
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invalid-VLD3DUPd32_UPD-thumb.txt
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A8.6.315 VLD3 (single 3-element structure to all lanes)
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2011-04-15 22:49:08 +00:00 |
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invalid-VLDMSDB_UPD-arm.txt
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Rename invalid-VLDMSDB-arm.txt to be invalid-VLDMSDB_UPD-arm.txt.
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2011-03-29 19:10:06 +00:00 |
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invalid-VQADD-arm.txt
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A7.3 register encoding
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2011-04-05 22:57:07 +00:00 |
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invalid-VST2b32_UPD-arm.txt
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A8.6.393
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2011-04-06 22:14:48 +00:00 |
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neon-tests.txt
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Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues to simplify the path towards an auto-generated disassembler.
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2011-07-15 18:46:47 +00:00 |
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thumb-printf.txt
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Disassembly of A8.6.59 LDR (literal) Encoding T1 (16-bit thumb instruction) should
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2011-04-22 19:12:43 +00:00 |
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thumb-tests.txt
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Disassembly of tBcc was wrongly adding 4 to the SignExtend'ed imm8:'0' immediate operand.
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2011-05-18 20:32:41 +00:00 |
43967a97cf