mirror of
https://github.com/c64scene-ar/llvm-6502.git
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72062f5744
This patch adds support for AArch64 (ARM's 64-bit architecture) to
LLVM in the "experimental" category. Currently, it won't be built
unless requested explicitly.
This initial commit should have support for:
+ Assembly of all scalar (i.e. non-NEON, non-Crypto) instructions
(except the late addition CRC instructions).
+ CodeGen features required for C++03 and C99.
+ Compilation for the "small" memory model: code+static data <
4GB.
+ Absolute and position-independent code.
+ GNU-style (i.e. "__thread") TLS.
+ Debugging information.
The principal omission, currently, is performance tuning.
This patch excludes the NEON support also reviewed due to an outbreak of
batshit insanity in our legal department. That will be committed soon bringing
the changes to precisely what has been approved.
Further reviews would be gratefully received.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174054 91177308-0d34-0410-b5e6-96231b3b80d8
124 lines
2.5 KiB
LLVM
124 lines
2.5 KiB
LLVM
; RUN: llc -verify-machineinstrs < %s -march=aarch64 -tailcallopt | FileCheck %s -check-prefix CHECK-TAIL
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; RUN: llc -verify-machineinstrs < %s -march=aarch64 | FileCheck %s
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; Without tailcallopt fastcc still means the caller cleans up the
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; stack, so try to make sure this is respected.
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define fastcc void @func_stack0() {
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; CHECK: func_stack0:
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; CHECK: sub sp, sp, #48
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; CHECK-TAIL: func_stack0:
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; CHECK-TAIL: sub sp, sp, #48
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call fastcc void @func_stack8([8 x i32] undef, i32 42)
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; CHECK: bl func_stack8
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; CHECK-NOT: sub sp, sp,
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; CHECK-TAIL: bl func_stack8
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; CHECK-TAIL: sub sp, sp, #16
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call fastcc void @func_stack32([8 x i32] undef, i128 0, i128 9)
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; CHECK: bl func_stack32
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; CHECK-NOT: sub sp, sp,
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; CHECK-TAIL: bl func_stack32
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; CHECK-TAIL: sub sp, sp, #32
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call fastcc void @func_stack0()
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; CHECK: bl func_stack0
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; CHECK-NOT: sub sp, sp
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; CHECK-TAIL: bl func_stack0
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; CHECK-TAIL-NOT: sub sp, sp
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ret void
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; CHECK: add sp, sp, #48
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; CHECK-NEXT: ret
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; CHECK-TAIL: add sp, sp, #48
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; CHECK-TAIL-NEXT: ret
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}
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define fastcc void @func_stack8([8 x i32], i32 %stacked) {
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; CHECK: func_stack8:
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; CHECK: sub sp, sp, #48
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; CHECK-TAIL: func_stack8:
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; CHECK-TAIL: sub sp, sp, #48
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call fastcc void @func_stack8([8 x i32] undef, i32 42)
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; CHECK: bl func_stack8
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; CHECK-NOT: sub sp, sp,
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; CHECK-TAIL: bl func_stack8
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; CHECK-TAIL: sub sp, sp, #16
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call fastcc void @func_stack32([8 x i32] undef, i128 0, i128 9)
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; CHECK: bl func_stack32
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; CHECK-NOT: sub sp, sp,
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; CHECK-TAIL: bl func_stack32
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; CHECK-TAIL: sub sp, sp, #32
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call fastcc void @func_stack0()
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; CHECK: bl func_stack0
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; CHECK-NOT: sub sp, sp
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; CHECK-TAIL: bl func_stack0
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; CHECK-TAIL-NOT: sub sp, sp
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ret void
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; CHECK: add sp, sp, #48
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; CHECK-NEXT: ret
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; CHECK-TAIL: add sp, sp, #64
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; CHECK-TAIL-NEXT: ret
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}
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define fastcc void @func_stack32([8 x i32], i128 %stacked0, i128 %stacked1) {
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; CHECK: func_stack32:
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; CHECK: sub sp, sp, #48
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; CHECK-TAIL: func_stack32:
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; CHECK-TAIL: sub sp, sp, #48
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call fastcc void @func_stack8([8 x i32] undef, i32 42)
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; CHECK: bl func_stack8
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; CHECK-NOT: sub sp, sp,
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; CHECK-TAIL: bl func_stack8
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; CHECK-TAIL: sub sp, sp, #16
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call fastcc void @func_stack32([8 x i32] undef, i128 0, i128 9)
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; CHECK: bl func_stack32
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; CHECK-NOT: sub sp, sp,
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; CHECK-TAIL: bl func_stack32
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; CHECK-TAIL: sub sp, sp, #32
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call fastcc void @func_stack0()
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; CHECK: bl func_stack0
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; CHECK-NOT: sub sp, sp
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; CHECK-TAIL: bl func_stack0
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; CHECK-TAIL-NOT: sub sp, sp
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ret void
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; CHECK: add sp, sp, #48
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; CHECK-NEXT: ret
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; CHECK-TAIL: add sp, sp, #80
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; CHECK-TAIL-NEXT: ret
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}
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