mirror of
https://github.com/c64scene-ar/llvm-6502.git
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73c5f80ec9
SPARC v9 extends all ALU instructions to 64 bits, so we simply need to add patterns to use them for both i32 and i64 values. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178527 91177308-0d34-0410-b5e6-96231b3b80d8
89 lines
1.6 KiB
LLVM
89 lines
1.6 KiB
LLVM
; RUN: llc < %s -march=sparcv9 | FileCheck %s
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; CHECK: ret2:
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; CHECK: or %g0, %i1, %i0
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define i64 @ret2(i64 %a, i64 %b) {
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ret i64 %b
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}
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; CHECK: shl_imm
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; CHECK: sllx %i0, 7, %i0
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define i64 @shl_imm(i64 %a) {
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%x = shl i64 %a, 7
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ret i64 %x
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}
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; CHECK: sra_reg
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; CHECK: srax %i0, %i1, %i0
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define i64 @sra_reg(i64 %a, i64 %b) {
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%x = ashr i64 %a, %b
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ret i64 %x
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}
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; Immediate materialization. Many of these patterns could actually be merged
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; into the restore instruction:
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;
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; restore %g0, %g0, %o0
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;
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; CHECK: ret_imm0
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; CHECK: or %g0, %g0, %i0
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define i64 @ret_imm0() {
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ret i64 0
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}
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; CHECK: ret_simm13
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; CHECK: or %g0, -4096, %i0
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define i64 @ret_simm13() {
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ret i64 -4096
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}
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; CHECK: ret_sethi
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; CHECK: sethi 4, %i0
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; CHECK-NOT: or
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; CHECK: restore
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define i64 @ret_sethi() {
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ret i64 4096
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}
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; CHECK: ret_sethi
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; CHECK: sethi 4, [[R:%[goli][0-7]]]
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; CHECK: or [[R]], 1, %i0
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define i64 @ret_sethi_or() {
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ret i64 4097
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}
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; CHECK: ret_nimm33
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; CHECK: sethi 4, [[R:%[goli][0-7]]]
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; CHECK: xor [[R]], -4, %i0
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define i64 @ret_nimm33() {
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ret i64 -4100
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}
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; CHECK: ret_bigimm
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; CHECK: sethi
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; CHECK: sethi
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define i64 @ret_bigimm() {
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ret i64 6800754272627607872
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}
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; CHECK: reg_reg_alu
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; CHECK: add %i0, %i1, [[R0:%[goli][0-7]]]
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; CHECK: sub [[R0]], %i2, [[R1:%[goli][0-7]]]
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; CHECK: andn [[R1]], %i0, %i0
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define i64 @reg_reg_alu(i64 %x, i64 %y, i64 %z) {
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%a = add i64 %x, %y
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%b = sub i64 %a, %z
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%c = xor i64 %x, -1
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%d = and i64 %b, %c
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ret i64 %d
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}
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; CHECK: reg_imm_alu
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; CHECK: add %i0, -5, [[R0:%[goli][0-7]]]
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; CHECK: xor [[R0]], 2, %i0
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define i64 @reg_imm_alu(i64 %x, i64 %y, i64 %z) {
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%a = add i64 %x, -5
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%b = xor i64 %a, 2
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ret i64 %b
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}
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